CMOS Image Sensor Pixel Integration via 3D Stacked Island Semiconductor
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in achieving high pixel integration due to the layout of photodiodes and transistors in a plane, limiting their density and efficiency.
Innovation Solution
A solid-state imaging device is designed with an island-shaped semiconductor structure on a Si substrate, featuring a p+-type diffusion layer, p-type impurity-doped region, and n+-type diffusion layer, where the charge storage section surrounds the p-type impurity-doped region, and the gate surrounds the p-type impurity-doped region through an insulating film, allowing for a combination of layers to function as a photodiode, amplification transistor, and reset transistor, enabling a more compact pixel design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photodiodes and transistors are arranged in a plane in conventional CMOS image sensors, then the device structure is simple and easy to manufacture, but the pixel integration degree is low and pixel density is limited
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacked arrangement of photodiodes and transistors. Multiple photodiodes are positioned at different heights above the substrate, with transistors connected to each photodiode in vertical layers, enabling high-density pixel integration while maintaining manufacturability through standard semiconductor fabrication processes
2Ease of manufacture
If photodiodes and transistors are arranged in a plane, then the manufacturing process is conventional and straightforward, but the unit pixel area is large and pixel density is low
Solution Approach 1:
By stacking photodiodes and transistors in vertical layers rather than arranging them side-by-side in a plane, the patent reduces the horizontal footprint of each pixel. Multiple functional elements occupy the same lateral space at different heights, thereby minimizing unit pixel area and increasing overall pixel density
Solution Approach 2:
The patent nests multiple photodiodes and transistors within a compact vertical structure where smaller components are positioned within or adjacent to larger ones in the vertical dimension. This nested arrangement allows all necessary pixel components to coexist in a small lateral footprint while maintaining proper electrical connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the formation of a CMOS image sensor with a high degree of pixel integration, achieving a unit pixel area of 4F^2, where F is the minimum fabrication size, thereby enhancing pixel density and imaging performance.
Implementation Method 1
a charge storage section comprised of a third semiconductor layer connected to the second semiconductor layer and adapted, in response to receiving light, to undergo a change in amount of electric charges therein
Data Source
Figure 1~2
Figure 3(a)~3(b)
Figure 4(a)~4(b)
AI summary
It is intended to provide a CMOS image sensor with a high degree of pixel integration. A solid-state imaging device comprises a signal line (256) formed on a Si substrate, an island-shaped semiconductor formed on the signal line, and a pixel selection line (255). The island-shaped semiconductor includes: a first semiconductor layer (252) connected to the signal line; a second semiconductor layer (251) located above and adjacent to the first semiconductor layer; a gate (253) connected to the second semiconductor layer through an insulating film; and a charge storage section comprised of a third semiconductor layer (254) connected to the second semiconductor layer and adapted, in response to receiving light, to undergo a change in amount of electric charges therein; a fourth semiconductor layer (250) located above and adjacent to the second and third semiconductor layers. The pixel selection line (255) is connected to the fourth semiconductor layer formed as a top portion of the island-shaped semiconductor.