CMOS Image Sensor Pixel Noise Reduction via Vertical Transistor and DTI
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Solution Overview
Problem
CMOS image sensors face challenges in reducing pixel noise due to increased integration density and decreased pixel size, which affects image quality.
Innovation Solution
The implementation of a deep trench isolation (DTI) structure and increased area of source follower transistors in each pixel, along with a wiring structure to connect transistors, enhances noise properties and reduces interference between adjacent pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased and pixel size is decreased, then productivity and device compactness are improved, but pixel noise increases and image quality deteriorates
Solution Approach 1:
The pixel structure is segmented into distinct functional regions: photoelectric conversion region, source follower transistor region, and floating diffusion region. This segmentation allows each region to be optimized independently, enabling the source follower transistor to have sufficient area for low noise operation while maintaining high integration density through efficient spatial arrangement.
Solution Approach 2:
The source follower transistor is configured with its channel extending in a direction substantially perpendicular to the substrate surface (vertical channel structure). This dimensional change allows the transistor to achieve sufficient effective area for low noise performance without occupying excessive planar space, thus resolving the contradiction between noise reduction and integration density.
2Area of stationary object
If pixel size is decreased, then device size is reduced, but area available for transistors decreases leading to increased noise
Solution Approach 1:
The source follower transistor utilizes a vertical channel structure where the channel extends perpendicular to the substrate. This allows the transistor effective area to be determined by channel length and width rather than requiring large planar footprint, enabling low noise operation in reduced pixel sizes.
Solution Approach 2:
The source follower transistor is nested within the pixel structure such that its source region overlaps with or is adjacent to the photoelectric conversion region, and its drain connects to the floating diffusion region. This nested arrangement maximizes space utilization within the pixel, allowing sufficient transistor area for noise reduction while maintaining compact pixel dimensions.
3Reliability
If transistors are made larger to reduce noise, then noise properties improve, but pixel area increases reducing integration density
Solution Approach 1:
The source follower transistor adopts a vertical channel configuration where current flows perpendicular to the substrate plane. This enables the transistor to achieve sufficient gate control and effective area for low noise operation without requiring large lateral dimensions, thus maintaining high integration density.
Solution Approach 2:
The transistor channel dimensions are locally optimized: channel length is set to provide sufficient gate control for low noise, while channel width and layout are optimized to fit within the pixel area. This local optimization allows the transistor to deliver noise performance comparable to larger planar transistors while occupying minimal pixel area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves pixel noise properties, leading to better image quality by decreasing noise levels and preventing electrical and optical crosstalk between pixels.
Implementation Method 1
Each of the unit pixels of a CMOS image sensor includes a photoelectric conversion unit and a charge transfer unit. The charge transfer unit transmits charge generated at the photoelectric conversion unit from incident light to a charge detection unit.
Data Source
AI summary
An image sensor includes a substrate having a first pixel region and a second pixel region adjacent to the first pixel region, a device isolation layer between the first pixel region and the second pixel region and isolating the first pixel region and the second pixel region from each other, a first transistor disposed in the first pixel region, a second transistor disposed in the second pixel region, and a wiring structure electrically connecting the first transistor and the second transistor. The device isolation layer has a deep trench isolation (DTI) structure which extends from a top surface toward a bottom surface of the substrate.