CMOS Image Sensor Resolution Adjustment Circuit
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Solution Overview
Problem
CMOS image sensors face challenges in maintaining high spatial resolution and image quality, especially at low light levels, due to pixel sub-sampling methods that result in lost image information and aliasing, and require complex analog circuit designs for pixel binning and averaging.
Innovation Solution
A photo-sensor image resolution adjustment apparatus that decimates the image sensor array into sub-groups, performs column averaging in high light environments, and row binning in low light environments, using a Bayer patterned pixel array with even and odd averaging capacitors and switches to selectively average light conversion electrical signals, reducing the need for on-chip memory and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel sub-sampling is used to reduce resolution, then output bandwidth is reduced, but spatial resolution is lost and aliasing is introduced
Solution Approach 1:
The patent combines multiple adjacent pixel signals through analog summation in the readout circuitry to create a reduced-resolution output. By merging signals from multiple pixels before digitization, the system achieves resolution reduction while preserving spatial information through the combined signal, avoiding the aliasing problems of digital sub-sampling.
Solution Approach 2:
The patent performs analog averaging of pixel signals in the readout circuitry before the signals are digitized and stored. This preliminary analog processing reduces the data volume early in the signal chain, decreasing the required output bandwidth and memory capacity while maintaining image quality through proper signal combination.
2Measurement precision
If pixel binning is implemented to maintain spatial resolution, then complex analog circuit design is required
Solution Approach 1:
The patent divides the pixel array into distinct groups or bins, where pixels within each bin are combined through analog summation. This segmentation approach allows independent processing of different regions, simplifying the overall circuit design by breaking down the complex binning operation into manageable segments that can be handled by standardized readout circuits.
Solution Approach 2:
The patent changes the operational parameters of the readout circuitry to enable analog signal combination. By adjusting the timing and control signals that govern pixel readout and summation, the system achieves binning functionality through parameter modification rather than requiring complex additional hardware circuitry.
3Measurement precision
If full resolution imaging is used, then image quality is maintained, but power consumption increases
Solution Approach 1:
The patent applies partial binning strategies where only certain regions or conditions trigger signal combination. By selectively binning pixels based on scene requirements rather than uniformly across the entire array, the system maintains full resolution where needed for high image quality while reducing power consumption through targeted resolution reduction in appropriate regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves high spatial resolution and image quality in both high and low light conditions with reduced pixel output rate and power consumption, while simplifying analog circuit design and eliminating the need for additional on-chip memory.
Implementation Method 1
Each sensor type detects unique colors of the light and converts the light to a light conversion electrical signals
Data Source
AI summary
A photo-sensor image resolution adjustment apparatus is in communication with an array of image photo-sensors that are organized in columns and rows and have multiple sensor types arranged in a pattern such as a Bayer pattern to detect light. The photo-sensor image resolution adjustment apparatus has a photo-sensor array decimation circuit to partition the array of image photo-sensors into a plurality of sub-groups. A column averaging circuit averages the light conversion electrical signals from common color photo-sensors within the sub-groups. A row averaging circuit averages the common color adjacent light conversion electrical signals from color adjacent rows within the sub-groups in high light intensity condition. In low light conditions, a row binning circuit integrates the common color adjacent light conversion electrical signals from color adjacent rows within the sub-groups.