CMOS Image Sensor Stacked Transistor Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in manufacturing high-quality CMOS image sensors is the difficulty in reducing the size of unit pixels while maintaining sensitivity due to the complexity of integrating transistors and wirings on light-sensitive areas, which can lead to noise and reduced signal-to-noise ratio.
Innovation Solution
The design incorporates pairs of photodiodes with a floating diffusion region, n-wells, and p-type impurity regions, along with transfer gates forming transfer transistors, and the use of transparent oxide semiconductor transistors for reset, source follower, and selection transistors, with carefully aligned output and power source lines to minimize noise and maximize signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistors and wirings are integrated on light receiving areas of photodiodes, then device functionality is improved, but noise increases and signal-to-noise ratio deteriorates
Solution Approach 1:
The patent moves transistors from the planar light receiving area to a vertical stacked configuration above the photodiode. This dimensional transition allows transistors to be positioned in the third dimension (vertical direction) rather than competing for two-dimensional planar space, eliminating the trade-off between functionality and noise.
Solution Approach 2:
The patent implements a stacked sensor architecture where multiple components (photodiode, transfer transistor, reset transistor, source follower transistor) are nested vertically one above another. This nesting allows all necessary functional elements to be contained within a compact vertical column, maintaining full device functionality while keeping the light receiving area clear.
2Productivity
If micro process is applied to reduce chip size, then productivity increases and unit cost decreases, but manufacturing high-quality sensors becomes difficult
Solution Approach 1:
The stacked configuration utilizes the vertical dimension to accommodate all transistor components, allowing planar photodiode arrays to be manufactured with high precision using standard micro processes while adding functional complexity through vertical stacking. This separates the precision requirements of photodiode fabrication from transistor integration.
Solution Approach 2:
The patent divides the sensor into distinct functional layers stacked vertically: photodiode layer for light detection, transfer transistor layer for charge transfer, reset transistor layer for signal resetting, and source follower transistor layer for signal amplification. This segmentation allows each layer to be optimized and manufactured separately with appropriate precision requirements.
3Productivity
If unit pixel size is reduced, then more pixels per chip increase productivity, but sensitivity deteriorates
Solution Approach 1:
By moving transistors to the vertical dimension through stacking, the patent frees up planar space in each pixel, allowing the light receiving area to be maximized even as overall pixel density increases. This enables smaller pixels to maintain adequate photodiode area for sensitivity.
Solution Approach 2:
The stacked configuration allows a single vertical column to contain multiple transistors that collectively provide all necessary functions (charge transfer, reset, amplification) that would otherwise require separate components. This multi-functionality within a compact vertical space enables higher pixel density without sacrificing per-pixel performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a smaller pixel size without compromising sensitivity, enabling the production of high-quality CMOS image sensors with improved signal-to-noise ratio and reduced noise, while also allowing for miniaturization of camera modules.
Implementation Method 1
a plurality of photodiodes 102 formed on a substrate 101
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
Provided is a complementary metal oxide semiconductor (CMOS) image sensor having a structure capable of increasing areas of photodiodes in unit pixels and expanding light receiving areas of the photodiodes. In the CMOS image sensor, transfer transistors may be formed on the photodiode, and reset transistors, source follower transistors, and selection transistors may be formed on a layer on which the transfer transistors are not formed. In such a CMOS image sensor, the areas of the photodiodes may be increased in unit pixels so that a size of the unit pixels may be reduced and sensitivity of the pixel may be improved.