CMOS Image Sensor Dark Current Reduction via Tensile Stress Engineering
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Solution Overview
Problem
As CMOS image sensors transition to finer sub-micron nodes, the reduction of dark current becomes critical due to increased compressive stress during shallow trench isolation (STI) creation, leading to higher dark current and white cell counts, which can render photodiodes inoperable.
Innovation Solution
A tensile stress layer is deposited over the active pixel cell to counteract the compressive stress introduced during STI creation, reducing dark current and white cell counts, and enhancing NMOS transistor mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If shallow trench isolation (STI) creation is performed during CMOS image sensor manufacturing, then device isolation and structural integrity are improved, but compressive stress increases leading to higher dark current and white cell counts
Solution Approach 1:
A tensile stress layer is deposited over the active pixel cell to counteract the compressive stress introduced during STI creation. This counterbalancing approach reduces the net compressive stress on the photodiode, thereby decreasing dark current and white cell counts while maintaining the structural benefits of STI isolation.
Solution Approach 2:
The patent modifies the stress state of the substrate by introducing a stress layer with specific tensile properties. By controlling the stress parameters (tensile stress magnitude and distribution), the patent optimizes the balance between structural integrity and dark current reduction, achieving lower dark current without compromising device isolation.
2Manufacturing precision
If pixel sizes are reduced to increase resolution, then imaging detail is improved, but dark current becomes more pronounced
Solution Approach 1:
The tensile stress layer serves as a counterbalancing element that offsets compressive stress effects, which become more significant in smaller pixels. By applying this counter-stress, the patent enables smaller pixel sizes to be used without proportionally increasing dark current, thus maintaining signal-to-noise ratio at higher resolutions.
3Object-affected harmful factors
If a tensile stress layer is deposited to reduce dark current, then dark current and white cell counts decrease, but device complexity increases
Solution Approach 1:
The stress layer is integrated into the existing CMOS image sensor manufacturing process as a multi-functional element. It simultaneously reduces dark current, controls white cell counts, and can be deposited using standard semiconductor fabrication techniques, thereby minimizing additional process complexity while achieving multiple performance benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The deposition of a tensile stress layer effectively decreases dark current and white cell counts by 7% and increases N-carrier mobility of NMOS transistors, improving the operational efficiency of CMOS image sensors.
Implementation Method 1
A tensile stress layer is deposited over the active pixel cell to counteract the compressive stress introduced during STI creation
Implementation Method 2
enhancing NMOS transistor mobility
Data Source
AI summary
A method of preparing an active pixel cell on a substrate includes exerting a first stress on the substrate by forming a shallow trench isolation (STI) structure in the substrate. The method further includes testing the stressed substrate using Raman spectroscopy at a plurality of locations on the stress substrate. The method further includes depositing a stress layer having a second stress on the substrate. The stress layer covers devices of the active pixel cell that are on the substrate and the devices include a photodiode next to the STI and a transistor, and the deposition of the stress layer results in the second stress being exerted on the substrate, the second stress countering the first stress.