CMOS Image Sensor Transistor Layout with Angled Edges
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Solution Overview
Problem
CMOS image sensors face challenges in maximizing photodiode area while minimizing die area and pixel count, as existing layouts often occupy excessive space with photodiode circuitry.
Innovation Solution
The layout of transistors and photodiodes in the image sensor is optimized by positioning reset, source follower, and read select transistors with angled edges between 30 and 60 degrees over the photodiodes, allowing for a more compact integration of circuitry atop the photodiodes, using vertical transfer gates and a common floating node diffusion, and employing 'U' or 'O' shaped transistors to enhance reading efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors are positioned with standard orthogonal layouts, then ease of manufacture is improved, but die area is excessive and photodiode area is reduced
Solution Approach 1:
The patent applies asymmetry by orienting transistor gates and shapes at angles of 30, 45, or 60 degrees relative to the photodiode row axis, rather than using standard orthogonal (0 or 90 degree) layouts. This angular orientation allows more efficient packing of transistors around the floating node, reducing the overall die area while maintaining manufacturability through standard fabrication processes.
Solution Approach 2:
The patent utilizes vertical stacking in the third dimension by positioning transfer gates, reset transistors, source follower transistors, and read select transistors at different vertical levels above the photodiodes. This 3D integration approach reduces the horizontal footprint on the die, allowing more photodiodes to be packed into the same area while keeping manufacturing processes standard.
2Productivity
If more circuitry is integrated per photodiode, then reading efficiency is improved, but die area increases
Solution Approach 1:
The patent merges multiple transistor functions into a compact arrangement around a shared floating node. The transfer gates, reset transistor, source follower transistor, and read select transistor are all integrated in close proximity and share common diffusion regions, reducing redundant circuitry and minimizing the area required per photodiode while maintaining full reading functionality.
Solution Approach 2:
The floating node diffusion serves multiple functions simultaneously: it acts as the charge collection node for photodiodes, the gate node for the source follower transistor, and the drain node for the reset transistor. This multi-functionality reduces the number of separate components needed, thereby reducing die area while improving reading efficiency through compact integration.
3Reliability
If photodiode area is maximized, then sensitivity is improved, but circuitry integration becomes difficult
Solution Approach 1:
The patent applies local quality by concentrating all necessary circuitry (transfer gates, reset transistor, source follower transistor, read select transistor) in a localized region directly above each photodiode or group of photodiodes. This localized integration allows the photodiode area to be maximized for sensitivity while the circuitry complexity is contained in a small, manageable footprint that does not interfere with photodiode performance.
Solution Approach 2:
By moving circuitry integration into the vertical dimension (stacking transistors above photodiodes rather than spreading them out horizontally), the patent enables larger photodiode areas to be used without increasing overall device complexity. The 3D integration separates the light-sensitive photodiode plane from the circuitry plane, allowing each to be optimized independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes die area usage, maximizes photodiode area, and improves reading speed while reducing noise, thereby enhancing the sensitivity and pixel count of the image sensor.
Implementation Method 1
CMOS image sensors face challenges in maximizing photodiode area
Data Source
AI summary
A CMOS image sensor has an array of photodiode cells, the photodiode cells each include four buried photodiodes coupled by vertical transfer gate transistors to a single floating node diffusion. Each cell also has a reset transistor coupled to the floating node diffusion, a source follower transistor having gate coupled to the floating node diffusion, and a read select transistor coupled to the source follower transistor. The reset transistor, source follower transistor, and read select transistor have predominately gate and shape edges oriented at an angle greater than 30-degrees and less than 60-degrees from a line extending along an entire horizontal row of photodiodes of a photodiode array of the image sensor and are formed vertically above, and in the same integrated circuit as, the photodiodes of the photodiode array.