Auto-Detecting CMOS Input Circuit for High-Voltage Handling
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Solution Overview
Problem
Conventional input circuits for integrated circuits (ICs) face challenges in handling high-voltage input signals without exposing internal transistors to electrical overstress, as they can only accommodate voltage levels up to twice the native supply voltage, requiring additional processing and more expensive dual-gate, dual-power-supply CMOS processes.
Innovation Solution
An auto-detecting input circuit with a cascading sequence of PMOS transistors and floating wells, along with well-bias selectors, is used to withstand external voltages exceeding the native supply voltage level, ensuring no gate oxide is exposed to excessive voltage, allowing the circuit to operate at elevated external signaling levels without damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional voltage level shifting techniques are used to sense external input signals, then input signal voltage levels up to two times VDD can be handled, but the circuit requires special gate constructs and additional processing
Solution Approach 1:
The input circuit is segmented into multiple stages with separate voltage domain handling. The first stage operates in the high-voltage domain to sense external signals, while the second stage operates in the native voltage domain for internal processing. This segmentation allows the circuit to handle voltages up to two times VDD without requiring complex special gate constructs throughout the entire circuit.
2Adaptability or versatility
If dual-gate, dual-power-supply CMOS process is used to handle voltages higher than two times the power supply voltage, then higher voltage tolerance is achieved, but manufacturing cost increases
Solution Approach 1:
The patent applies different voltage tolerance characteristics to different parts of the circuit based on their functional requirements. Only the input sensing portion requires high-voltage tolerance, while the internal logic circuits operate at the native voltage level. This local differentiation allows the circuit to achieve high voltage tolerance where needed without incurring the full cost of a dual-power-supply CMOS process across the entire device.
3Adaptability or versatility
If the input circuit operates at elevated external signaling-voltage levels, then broader voltage range operation is enabled, but internal transistors may be exposed to electrical overstress
Solution Approach 1:
The patent introduces an intermediary voltage domain and level-shifting mechanisms between the high-voltage external signaling domain and the native voltage domain where internal transistors operate. This intermediary structure allows the circuit to accept elevated external voltages while preventing electrical overstress to internal transistors by systematically reducing voltage levels at each stage of signal transmission.
Data Source
AI summary
An auto-detecting input circuit is operative to sustain relatively high voltages applied to an input pad and generate corresponding signal levels at a native supply voltage range. The input circuit includes floating wells, corresponding bias selectors, and input biasing transistors to ensure that no gate oxide exposed to external voltages sustains a voltage greater than a predefined value. Bias selectors select an available highest voltage to reverse bias corresponding floating wells and ensure transistors are not electrically overstressed. As input-related terminals experience switching related voltages, the bias selectors select alternate terminals to continue selection of the highest voltage available and provide correct reverse biasing conditions. A resistor and clamp generate translated output voltage levels limited to the native supply voltage range. A latch is triggered by a first input signal excursion above the native supply voltage. The latch output enables pull-down transistors to provide a correct low-level output signal.