CMOS Interconnect Layout for Electromigration Mitigation
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Solution Overview
Problem
Electromigration (EM) in CMOS devices leads to the gradual movement of ions, causing connection loss and reliability issues in integrated circuits, necessitating effective layout constructions to mitigate these effects.
Innovation Solution
The proposed solution involves a CMOS device layout where PMOS and NMOS transistors are interconnected through specific interconnects on multiple levels, with subsets of drains connected and disconnected in a manner that increases back stress and allows bidirectional current flow, reducing EM by limiting interconnect lengths and providing parallel current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If interconnect lengths are increased to connect more drains, then device complexity is reduced, but electromigration degradation increases
Solution Approach 1:
The interconnect structure is segmented into multiple shorter interconnects (first interconnect, second interconnect, third interconnect, fourth interconnect) that connect different subsets of drains. Each interconnect has a limited length to reduce electromigration, while the segments are combined through multiple interconnect levels to achieve the overall connection function.
Solution Approach 2:
The patent uses multiple interconnect levels (first interconnect level, second interconnect level) to connect drains. By adding the vertical dimension with multiple levels, the design achieves long-distance connectivity without requiring any single horizontal interconnect to be excessively long, thus reducing electromigration in each individual interconnect.
2Device complexity
If single-direction current flow is used in interconnects, then circuit design is simplified, but electromigration increases
Solution Approach 1:
The patent configures the interconnects so that current flows in opposite directions through different interconnects. Specifically, the first and third interconnects carry current in one direction while the second and fourth interconnects carry current in the opposite direction. This bidirectional current flow creates opposing electron wind forces that counteract electromigration, improving reliability without significantly increasing design complexity.
3Reliability
If interconnects are disconnected on the interconnect level, then electromigration is reduced, but device complexity increases
Solution Approach 1:
The patent disconnects interconnects on the first interconnect level (first interconnect disconnected from second interconnect; third interconnect disconnected from fourth interconnect) to limit current path lengths and reduce electromigration. The segmentation is managed by introducing additional interconnects on the second interconnect level that bridge the disconnected segments, achieving both electromigration reduction and functional connectivity.
Solution Approach 2:
The second interconnect level acts as an intermediary between the disconnected interconnects on the first level. The fifth interconnect and sixth interconnect on the second level provide alternative current paths that connect the otherwise disconnected first/second and third/fourth interconnects, enabling the design to achieve both electromigration reduction through disconnection and functional connectivity through the intermediary level.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces EM degradation by increasing mechanical stress and enabling bidirectional electron wind, thereby enhancing the reliability of CMOS devices by allowing higher operational frequencies without violating EM compliance.
Implementation Method 1
EM is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms
Implementation Method 2
the momentum transfer between conducting electrons and diffusing metal atoms
Data Source
AI summary
A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.