CMOS Interconnect Layout for Electromigration Mitigation
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Solution Overview
Problem
Electromigration (EM) in CMOS devices leads to the gradual movement of ions, causing connection loss and reliability issues in integrated circuits, necessitating effective layout constructions to mitigate these effects.
Innovation Solution
The layout construction involves interconnecting subsets of PMOS and NMOS transistors with specific interconnects on different levels, ensuring disconnection on one level and coupling through other levels, reducing interconnect lengths and promoting bidirectional current flow to increase mechanical stress and back stress, thereby addressing EM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If interconnects are made longer to connect more transistors, then device functionality is improved, but electromigration degradation increases
Solution Approach 1:
The patent divides the interconnect system into multiple separate interconnects on the same level, each connecting to different subsets of transistor drains. These interconnects are disconnected from each other at their intersections, preventing current accumulation and reducing electromigration stress while maintaining connectivity to multiple transistors.
Solution Approach 2:
The patent uses multiple interconnect levels (vertical stacking) to provide alternative current paths. By coupling interconnects through vias to subsequent levels, current can flow in multiple directions (bidirectional electron wind), which balances stress and reduces electromigration degradation without requiring longer interconnects.
2Power
If interconnect length is increased to connect more drains, then current capacity is improved, but mechanical stress and electromigration increase
Solution Approach 1:
Multiple shorter interconnects are used instead of one long interconnect. Each interconnect connects to a subset of drains, distributing the current load across multiple paths. This segmentation reduces the mechanical stress on each individual interconnect while maintaining overall current capacity through parallel paths.
Solution Approach 2:
The patent enables bidirectional current flow through the multi-level interconnect structure. Current can flow in opposite directions through different interconnects and levels, creating dynamic stress balancing that reduces cumulative mechanical stress and electromigration effects compared to unidirectional flow in a single long interconnect.
3Device complexity
If all PMOS and NMOS drains are connected on the same interconnect level, then layout simplicity is improved, but electromigration compliance deteriorates
Solution Approach 1:
The patent segments the interconnect system into multiple disconnected interconnects on the same level, each serving specific subsets of PMOS and NMOS drains. This segmentation maintains relatively simple layout within each interconnect while ensuring EM compliance by preventing current accumulation that would occur in a single connected interconnect structure.
Solution Approach 2:
The patent introduces vias and additional interconnect levels as intermediary elements to couple the segmented interconnects. These intermediaries provide alternative current paths that satisfy EM compliance requirements while maintaining functional connectivity, effectively mediating between the simplicity of same-level connections and the reliability of EM-compliant design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces EM-induced degradation by increasing the mechanical stress on interconnects and allowing bidirectional electron wind, enhancing the reliability of CMOS devices by increasing the maximum allowed direct current without violating EM compliance.
Implementation Method 1
EM is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms
Implementation Method 2
allowing bidirectional electron wind, enhancing the reliability of CMOS devices by increasing the maximum allowed direct current without violating EM compliance
Data Source
AI summary
A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.