CMOS Interface Circuit With Input Level Fixing for SSTL Signals
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Solution Overview
Problem
In semiconductor devices, small-amplitude signal interfaces like SSTL face issues with power consumption and circuit stability due to the use of differential amplification circuits, which lead to erroneous signal recognition and potential variations during high-impedance states, making it difficult to replace with CMOS circuits without causing circuit destruction or erroneous operations.
Innovation Solution
An interface circuit is designed with an input buffer gate formed of a circuit other than differential amplification circuits, utilizing a resistance circuit to fix the potential level during signal no-supply modes and remove fixation during signal output and input modes, eliminating the need for reference voltages and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a differential amplification circuit is used as the input buffer gate, then small-amplitude signals can be received at high speed, but power consumption increases due to through current flowing all the time
Solution Approach 1:
The patent changes the operational state of the input buffer gate by switching between high-impedance state (during data transmission) and active state (during idle periods). This parameter change allows the circuit to maintain high-speed reception capability when needed while minimizing power consumption during idle periods by eliminating through current flow.
Solution Approach 2:
The patent makes the input buffer gate dynamic by controlling its impedance state based on operational requirements. The gate transitions from a static always-active differential amplification circuit to a dynamic circuit that switches between high-impedance and active states, optimizing both speed and power consumption characteristics.
2Use of energy by moving object
If the input buffer gate is in high-impedance state during idle periods, then power consumption is reduced, but the voltage level becomes unstable and may cause erroneous signal recognition
Solution Approach 1:
The patent introduces a terminal resistor RT as an intermediary element that maintains stable voltage levels at the input buffer gate even when the gate is in high-impedance state. This mediator component ensures that the voltage remains at a defined level (VDDQ/2) during idle periods, preventing erroneous signal recognition while allowing power savings from the high-impedance state.
Solution Approach 2:
The patent prepares for potential voltage instability by using the terminal resistor to establish a predetermined voltage level in advance during idle periods. This prior cushioning ensures that when the buffer gate transitions from high-impedance to active state, the voltage is already stabilized and ready for accurate signal recognition, preventing erroneous operations.
3Reliability
If a terminal resistor is added to stabilize voltage levels, then signal recognition accuracy improves, but device complexity and circuit scale increase
Solution Approach 1:
The patent makes the terminal resistor RT multi-functional by having it serve both as a voltage stabilization element during high-impedance periods and as part of the signal reception circuit during active periods. This universal component performs multiple functions (voltage reference, signal termination, and level setting) without requiring separate dedicated components, thereby minimizing circuit scale increase while maintaining signal recognition accuracy.
4Use of energy by moving object
If CMOS circuits are used instead of differential amplification circuits, then power consumption is reduced, but the circuits cannot handle small-amplitude signals effectively
Solution Approach 1:
The patent makes the CMOS-based input buffer gate dynamic by switching between high-impedance state and active state. During active state, the CMOS circuit effectively detects small-amplitude signals; during idle periods, it transitions to high-impedance state to minimize power consumption. This dynamic operation allows CMOS circuits to achieve both low power consumption and effective small-signal detection capability.
Solution Approach 2:
The patent prepares the CMOS input buffer gate by establishing a stable voltage level through the terminal resistor before signal reception begins. This preliminary action ensures that the CMOS circuit starts from a known stable state, enabling it to effectively detect small-amplitude signals when activated, while maintaining low power consumption during idle periods.
Data Source
AI summary
An interface circuit is provided for use in a semiconductor device which transmits and receives a signal to and from the outside. The interface circuit includes a signal input/output terminal for receiving a signal from the outside in a signal input mode and a signal from the semiconductor device in a signal output mode, an input buffer gate circuit having an input terminal connected to the signal input/output terminal and for outputting a signal received at the input terminal to the semiconductor device, and an input level control circuit for fixing a potential level at the input terminal of the input buffer gate circuit to a predetermined level in a signal no-supply mode and removing the fixation of the potential level in the signal output mode and in the signal input mode.