CMOS Inverter With Common Gate Structure and Vertical Stacking
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Solution Overview
Problem
The existing CMOS inverter circuit technology requires a larger horizontal area on the substrate due to the separate formation of N-type and P-type transistors, which limits the integration density of semiconductor devices.
Innovation Solution
A semiconductor device with a buried insulation layer and vertically stacked impurity regions, where N-type and P-type transistors share a common gate structure, allowing for a compact CMOS inverter circuit formation on a smaller substrate area by using a common gate structure and conductive patterns to connect the transistors efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If N-type and P-type transistors are formed separately on the substrate in horizontal span, then the CMOS inverter circuit can be formed with proper transistor separation, but the horizontal area of the substrate is increased
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical stacking by forming N-type and P-type transistors in different vertical levels on the substrate. The first transistor is formed at a first vertical level while the second transistor is formed at a second vertical level, allowing both transistors to occupy overlapping horizontal footprints while maintaining proper separation through vertical positioning. This dimensional change resolves the contradiction by enabling compact integration without compromising transistor separation requirements.
Solution Approach 2:
The patent implements a nested structure where the second transistor is formed within the vertical projection area of the first transistor. The active region, gate electrode, and source/drain regions of the second transistor are positioned such that they nest within the horizontal footprint of the first transistor's corresponding structures. This nesting approach allows both transistors to coexist in a compact area while maintaining electrical isolation through vertical separation and insulation layers.
2Area of stationary object
If N-type and P-type transistors are formed in vertical stack with common gate structure, then the substrate area is reduced, but the device structure complexity is increased
Solution Approach 1:
The patent divides the vertical stack into distinct functional segments separated by insulation layers. Each transistor is segmented into active regions, gate electrodes, and source/drain regions that are vertically stacked but horizontally separated by insulating structures. The first and second insulating layers create clear segmentation between the N-type and P-type transistor components, making the complex vertical structure manageable through systematic division into isolated functional units.
Solution Approach 2:
The patent introduces insulating layers as intermediary structures between the N-type and P-type transistor components. These insulating layers act as mediators that provide electrical isolation while allowing the transistors to be vertically stacked. The first and second insulating layers serve as intermediary barriers that enable the complex vertical integration without direct electrical contact between opposing transistor components, simplifying the overall device fabrication and operation.
Data Source
AI summary
A semiconductor device includes a buried insulation layer pattern on a lower substrate. A first semiconductor pattern and a second semiconductor pattern pattern are disposed on on the buried insulation layer pattern. A lower conductive pattern is formed in a lower portion of a first recess between the first and second semiconductor patterns, and the lower conductive pattern may contact lower sidewalls of the first and second semiconductor patterns. A common gate structure formed on the lower conductive pattern fills a remaining portion of the first recess. The first semiconductor pattern may include a first impurity region, a first channel region, and a second impurity region sequentially stacked from an upper surface of the first semiconductor towards the lower substrate. The second semiconductor pattern includes a third impurity region, a second channel region, and a fourth impurity region.