CMOS Inverter Gate Delay Paths to Minimize Short-Circuit Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS inverter circuits generate short circuit currents when input signals transition, leading to increased power consumption and potential damage to circuit elements, and existing methods to minimize these currents compromise working speed and circuit complexity.
Innovation Solution
A CMOS inverter circuit design that includes a delay circuit unit with PMOS and NMOS transistors, allowing for independent charging and discharging paths for gate nodes, preventing simultaneous switching of PMOS and NMOS transistors during signal transitions, thereby minimizing short circuit currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a CMOS inverter circuit uses conventional simultaneous switching of PMOS and NMOS transistors, then the circuit complexity is low and the working speed is high, but short circuit current is generated leading to increased power consumption
Solution Approach 1:
The patent divides the switching control into separate paths for PMOS and NMOS transistors. The gate node of PMOS is discharged through transistor M4, while the gate node of NMOS is discharged through transistor M5, creating independent control segments that prevent simultaneous conduction and reduce short circuit current
Solution Approach 2:
The patent implements preliminary discharge actions before the main switching operation. Transistor M4 discharges the PMOS gate node first, and transistor M5 discharges the NMOS gate node first, ensuring that the transistors are turned off before the input signal completes its transition, thereby preventing short circuit current
2Loss of energy
If a CMOS inverter circuit implements simultaneous turning-off of PMOS and NMOS to minimize short circuit current, then power consumption is reduced, but the circuit architecture becomes more complex with additional transistors and feedback loops
Solution Approach 1:
The patent merges the discharge functions into a single transistor M4 that handles both PMOS gate discharge, and uses transistor M5 for NMOS gate discharge. This consolidated approach achieves simultaneous turning-off functionality while minimizing the number of additional components required
Solution Approach 2:
The patent introduces transistor M4 as an intermediary element that mediates the discharge of the PMOS gate node, and transistor M5 that mediates the discharge of the NMOS gate node. These intermediary transistors enable controlled sequential switching without requiring complex feedback loops
3Loss of energy
If a CMOS inverter circuit adds delay circuit units with additional PMOS and NMOS transistors for independent charging and discharging paths, then short circuit current is minimized, but the circuit complexity increases
Solution Approach 1:
The patent designs transistor M4 to serve multiple functions: it discharges the PMOS gate node during switching transitions and also provides a discharge path for the NMOS gate node. Similarly, transistor M5 handles both PMOS and NMOS gate discharge functions, reducing the need for dedicated separate transistors for each function
Data Source
AI summary
There is provided a CMOS inverter circuit device. The CMOS inverter circuit device includes a delay circuit unit configured to generate different charge and discharge paths of each gate node of a PMOS transistor and an NMOS transistor respectively at the time that an input signal transitions between high and low levels. Therefore, the present examples minimize or erase generation of a short circuit current made at the time that the input signal transition. The examples may simplify circuit architecture, and may make a magnitude of a CMOS inverter circuit device smaller.