CMOS Inverter Gate Structure Reducing Parasitic Capacitance
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased parasitic capacitance and electrical resistance at the boundary area between PMOS and NMOS regions, causing deterioration in AC performance due to the short channel effect and current leakage.
Innovation Solution
A semiconductor device design with a substrate divided into areas with different conductivity types, featuring distinct gate structures on active lines and a boundary area with a dielectric constant and metal gate composition that reduce parasitic capacitance and electrical resistance, including a third gate structure with a lower dielectric constant and single metal layer on the device isolation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the line width of the gate electrode is reduced to minimize occupied area, then device miniaturization is achieved, but parasitic capacitance increases at the boundary area between PMOS and NMOS
Solution Approach 1:
The patent applies different dielectric materials with different dielectric constants to different regions: high dielectric constant materials (first and second dielectric layers) are used in the PMOS and NMOS active regions, while a low dielectric constant material (third dielectric layer) is specifically used in the boundary area between PMOS and NMOS. This local differentiation reduces parasitic capacitance at the boundary without increasing the overall occupied area of the gate electrode.
2Volume of moving object
If miniaturization is pursued to increase integration density, then device size is reduced, but electrical resistance increases due to shorter channel length
Solution Approach 1:
The patent changes the dielectric parameter (dielectric constant) in the boundary area by using a third dielectric layer with lower dielectric constant than the first and second dielectric layers. This parameter change reduces parasitic capacitance and electrical resistance in the boundary region, allowing device miniaturization without proportionally increasing resistance.
3Productivity
If the gate electrode occupies minimal area for high integration, then manufacturing density increases, but AC performance deteriorates due to increased parasitic capacitance
Solution Approach 1:
The patent uses local quality differentiation by applying a low dielectric constant third dielectric layer specifically in the boundary area, while maintaining high dielectric constant materials in the active regions. This localized approach reduces parasitic capacitance that degrades AC performance, enabling high integration density without sacrificing AC performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces parasitic capacitance and electrical resistance, enhancing the AC performance of the CMOS inverter by minimizing the short channel effect and current leakage, while maintaining stable device operation.
Implementation Method 1
a third dielectric layer having a dielectric constant smaller than those of the first and the second dielectric layers
Implementation Method 2
a third metal gate that may be arranged on the third dielectric layer
Data Source
AI summary
Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device isolation layer, the substrate being divided into an NMOS area, a PMOS area and a boundary area interposed between the NMOS and the PMOS areas and having the device isolation layer without the active line, a gate line extending in a second direction across the active lines and having a first gate structure on the active line in the first area, a second gate structure on the active line in the second and a third gate structure on the device isolation layer in the third area. The electrical resistance and parasitic capacitance of the third gate structure are smaller than those of the NMOS and the PMOS gate structures. Accordingly, better AC and DC performance of the CMOS device can be obtained.