CMOS I/O Transistor VT Control via Blanket Implant and Masking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming CMOS semiconductor devices with dual supply voltage transistors face challenges in setting optimal threshold voltage for I/O transistors, leading to performance degradation due to high electrical fields and the need for additional masks, which complicates fabrication and fails to meet performance and lifetime specifications.
Innovation Solution
A method involving blanket implantation of P-type and N-type dopants in I/O transistors to set their threshold voltage, followed by masking to form NWELL and PWELL regions without using additional masks, allowing for separate control of logic and I/O transistor formation and optimizing threshold voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If identical implants are used for both low voltage and high voltage transistors, then fabrication is simplified, but I/O transistor threshold voltage becomes too high and performance degrades
Solution Approach 1:
The patent segments the implantation process into separate steps for logic transistors and I/O transistors. First, a blanket implant is performed to set the I/O transistor threshold voltage, then selective implants are performed for logic transistors while masking I/O transistors. This segmentation allows each transistor type to receive optimized doping without requiring additional masks beyond the standard process masks.
Solution Approach 2:
The patent performs the I/O transistor threshold voltage implantation as a preliminary blanket implant before the logic transistor selective implants. By setting the I/O transistor threshold voltage first, the subsequent logic transistor implants can be performed with standard masking techniques without affecting the already-set I/O transistor characteristics.
2Manufacturing precision
If additional masks are used to optimize both logic and I/O transistors, then threshold voltage control is improved, but fabrication complexity increases
Solution Approach 1:
The patent makes the standard process masks multi-functional by designing them to simultaneously define logic transistor regions and protect I/O transistor regions during selective implantation steps. The same masks used for logic transistor formation also serve to mask I/O transistors during their threshold voltage adjustment, eliminating the need for dedicated additional masks.
Solution Approach 2:
The patent merges the I/O transistor threshold voltage adjustment step with the existing logic transistor implantation sequence. By integrating the blanket implant and selective implant steps into the standard process flow, the solution combines multiple functions (I/O VT setting, logic transistor formation, and selective doping) into a unified fabrication sequence without adding separate mask layers.
3Productivity
If high doping is used for logic transistors, then logic transistor performance is optimized, but I/O transistor electrical field becomes too high
Solution Approach 1:
The patent applies local quality by giving different doping characteristics to different regions. The blanket implant provides a base doping level for I/O transistors, while the selective logic transistor implants provide additional localized doping only where needed for logic performance. This creates spatially varying doping concentrations that optimize each region's performance without compromising the other.
Solution Approach 2:
The patent performs preliminary anti-action by setting the I/O transistor threshold voltage first with a blanket implant, establishing a protective baseline that prevents subsequent logic transistor doping from adversely affecting I/O transistor electrical fields. This preliminary step counteracts the potential harmful effect of high doping on I/O reliability before the logic transistor optimization implants are performed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of CMOS devices with suitable I/O transistor threshold voltage without additional masks, improving performance and meeting specifications by separating the formation and voltage control of logic and I/O transistors, thus enhancing the overall efficiency of the semiconductor device fabrication process.
Implementation Method 1
A threshold voltage (VT) of the I/O NMOS transistor can then be set by implanting a P-type dopant in the I/O NMOS transistor; and a threshold voltage (VT) of the I/O PMOS transistor can be set by implanting an N-type dopant in the I/O PMOS transistor
Data Source
AI summary
Various embodiments provide methods for fabricating dual supply voltage CMOS devices with a desired I/O transistor threshold voltage. The dual supply voltage CMOS devices can be fabricated in a semiconductor substrate that includes isolated regions for a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor. Specifically, the fabrication can first set and/or adjust the threshold voltage (VT) of each of the I/O NMOS transistor and the I/O PMOS transistor to a desired level. Logic NMOS and logic PMOS transistors can then be formed with I/O NMOS and I/O PMOS transistors masked without affecting the set/adjusted VT of the I/O transistors.