CMOS Fin Structure With Isolation Fin for Threshold Voltage Stability
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Solution Overview
Problem
Existing semiconductor structures face instability in threshold voltage due to mutual influence between work function layers, leading to poor performance in CMOS transistors as the integration density of integrated circuits increases and feature sizes decrease.
Innovation Solution
A semiconductor structure with a third fin formed over an isolation region between first and second fins, blocking the work function layers and reducing mutual influence, while maintaining a controlled contact area to stabilize threshold voltages, using materials like TiN, TaN, and TiAl for the work function layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If work function layers are disposed adjacent to each other over different regions, then threshold voltage adjustment is achieved, but mutual influence between work function layers causes threshold voltage instability
Solution Approach 1:
A third fin structure is introduced as an intermediary element disposed over the isolation region between the first and second fins. This third fin acts as a physical barrier that blocks the mutual influence between the first and second work function layers, preventing their harmful interaction while allowing each to independently adjust the threshold voltage of its respective transistor.
Solution Approach 2:
The substrate is divided into distinct regions (first region, second region, and isolation region) with corresponding fins (first fin, second fin, and third fin). The third fin segmented from the other structures and positioned over the isolation region creates spatial separation that isolates the work function layers, eliminating their mutual interference.
2Productivity
If integration density increases and feature size decreases, then circuit density improves, but threshold voltage stability deteriorates due to work function layer mutual influence
Solution Approach 1:
The solution addresses the two-dimensional planar constraint by introducing a vertical dimension element - the third fin extending upward from the isolation region. This vertical structure blocks the lateral mutual influence between work function layers without occupying additional planar space, thus maintaining high integration density while improving threshold voltage stability.
Data Source
AI summary
A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate. The substrate includes a first region, a second region, and an isolation region between the first region and the second region. The semiconductor structure also includes a first fin, a second fin and a third fin disposed over the first region, the second region, and the isolation region, respectively. Further, the semiconductor structure includes a gate structure. The gate structure includes a first work function layer over the first region and a first portion of the isolation region, and a second work function layer over the second region and a second portion of the isolation region. An interface where the first work function layer is in contact with the second work function layer is located over a top surface of the third fin.