CMOS Image Sensor JFET Sensing Node Integration
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Solution Overview
Problem
Current CMOS image sensors face challenges in improving integration degree and signal-noise ratio, particularly in effectively converting optical signals into electrical signals with reduced noise and increased sensitivity.
Innovation Solution
The proposed CMOS image sensor employs a three-transistor structure with a photodiode, a transfer transistor, a reset transistor, and a selection transistor, utilizing a floating sensing node with dopant regions of different conductivity types to operate as a junction field effect transistor, allowing for improved signal conversion and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional CMOS image sensor structure is used, then the device complexity is reduced and manufacturing is easier, but the integration degree is limited and the fill factor is smaller
Solution Approach 1:
The invention merges the sensing node and the JFET gate into a single integrated structure. The sensing node is formed by doping a region within the JFET gate, combining two previously separate components (sensing node and gate) into one unified element, thereby increasing the fill factor without proportionally increasing device complexity
Solution Approach 2:
The JFET gate structure serves multiple functions: it acts as both the gate control element and the sensing node for detecting photocharges. This multi-functionality allows the same structure to perform both signal detection and transistor control, improving integration degree while maintaining manageable device complexity
2Measurement precision
If the sensing node area is increased to improve photocharge detection, then the signal-noise ratio improves, but the device area increases and integration degree decreases
Solution Approach 1:
By merging the sensing node with the JFET gate, the patent enables the sensing area to be effectively increased within the existing transistor footprint. The doped region within the gate structure serves as both the gate and the sensing node, allowing improved photocharge detection capability without requiring additional device area or increasing overall device complexity
3Reliability
If more transistors are added to improve signal conversion capability, then the output signal quality improves, but the device area increases and integration degree decreases
Solution Approach 1:
The JFET structure provides enhanced signal conversion capability through its junction field effect mechanism while occupying the same area as a conventional transistor. The multi-functional design where the gate serves as both gate and sensing node allows for improved signal conversion without adding extra transistors or increasing device area, thereby maintaining high integration degree
4Illumination intensity
If the fill factor is increased to improve light sensitivity, then the optical signal detection capability improves, but the area available for other circuit components decreases
Solution Approach 1:
The merger of the sensing node and JFET gate creates a compact structure that maximizes the light-sensitive area within the transistor footprint. By making the gate itself the sensing element, the design eliminates the need for separate sensing node structures, thereby increasing the fill factor and light sensitivity without encroaching on the area needed for other essential circuit components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integration degree and signal-noise ratio, reduces random telegraph signal and thermal noise, and increases the fill factor of the image sensor, leading to improved sensitivity and output quality.
Implementation Method 1
a photodiode configured to convert a received optical signal into photo charges
Data Source
AI summary
An image sensor includes a sensing node to sense photo charges output from a photodiode. The sensing node includes a first dopant region of a first conductivity type and a second dopant region of a second conductivity type. The second dopant region surrounds the first dopant region. A third dopant region of the first conductivity type is adjacent to the second dopant region and is disposed around the sensing node. The first, second, and third dopant regions operate as a source, a gate, and a drain of a junction field effect transistor, respectively.