CMOS Latch-Up Prevention via Dynamic Well Voltage Control
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Solution Overview
Problem
CMOS circuits are susceptible to latch-up during power-on due to parasitic devices being activated by forward-biased p-n junctions when multiple voltage supplies are ramped up at different rates, leading to high current flow and potential circuit damage, and existing solutions require larger chip areas to prevent latch-up by prohibiting well sharing.
Innovation Solution
A power supply switch system that compares voltage levels between lower and higher supply buses and routes current from the lower bus to the higher bus if the higher bus is not ready, using a voltage sensor and switch module to prevent latch-up, allowing for shared wells and reducing chip area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple n-wells are employed to prevent latch-up, then latch-up prevention is improved, but chip area increases due to well-to-well spacing requirements
Solution Approach 1:
The patent merges multiple n-wells into a single shared n-well structure, allowing multiple pMOS devices to share the same well. This is combined with a control mechanism that monitors voltage levels and activates protective measures only when necessary, thus reducing the total well area while maintaining latch-up prevention capability.
Solution Approach 2:
The patent changes the operational parameters of the shared n-well by dynamically adjusting its voltage level based on the power-on state of different voltage supplies. A voltage sensor monitors the voltage levels, and when a lower voltage supply is detected to be higher than a higher voltage supply, the n-well voltage is adjusted to prevent forward biasing of p-n junctions, thereby preventing latch-up without requiring multiple separate wells.
2Area of stationary object
If a single n-well is used to save silicon area, then chip area is reduced, but latch-up risk increases due to prohibited well sharing
Solution Approach 1:
The patent introduces dynamic control of the shared n-well voltage level. Instead of a static well structure, the n-well voltage is dynamically adjusted based on real-time monitoring of supply voltage levels. When latch-up conditions are detected (lower voltage supply higher than higher voltage supply), the n-well voltage is modified to prevent forward biasing, thus enabling safe well sharing while maintaining reliability.
Solution Approach 2:
The patent implements a feedback mechanism where a voltage sensor continuously monitors the voltage levels of different power supplies. When the sensor detects that a lower voltage supply has become higher than a higher voltage supply, it triggers a control signal to adjust the n-well voltage, creating a closed-loop feedback system that prevents latch-up conditions while allowing shared well usage.
3Reliability
If higher voltage supply is ramped up slower than lower voltage supply, then latch-up is prevented, but power-on time increases
Solution Approach 1:
The patent takes preliminary action by monitoring voltage levels during the power-on sequence and proactively adjusting the n-well voltage before latch-up conditions can develop. The voltage sensor detects potential latch-up conditions early, and the control mechanism preemptively modifies the n-well voltage to prevent forward biasing, allowing faster power-on without waiting for sequential voltage ramping.
Solution Approach 2:
The real-time feedback from the voltage sensor enables immediate detection and correction of potential latch-up conditions during power-on. When voltage level reversals are detected, the control system instantly adjusts the n-well voltage, eliminating the need for delayed sequential ramping and reducing overall power-on time while maintaining latch-up prevention.
Data Source
AI summary
There is provided a method for managing a multi-level power supply. The method includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2<Vs1. The lower and higher voltage supply busses provide power to a complementary metal oxide semiconductor (CMOS) circuit. The method prevents a latch-up of the CMOS circuit. There is also provided a circuit that employs the method.