CMOS Protection Circuit Using Resistive Shunts Against Latch-Up
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS integrated circuits face latch-up issues due to parasitic P/N/P/N structures, which can lead to undesirable conduction and destruction of the circuits, and existing guard ring and pick-up structures consume significant layout area.
Innovation Solution
Incorporating a shunt path with resistive loads to discharge minority carriers, increasing the voltage required to turn on the silicon controlled rectifier (SCR), thereby preventing undesired conduction and improving latch-up immunity without the need for large layout areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If guard ring structure and/or pick-up structure are applied to prevent latch-up, then latch-up immunity is improved, but layout area increases significantly
Solution Approach 1:
The patent modifies the electrical parameters of the CMOS circuit by introducing resistive loads that alter the voltage thresholds and current characteristics. This changes the operating parameters to prevent latch-up without requiring additional physical structures, thereby maintaining reliability while reducing layout area.
Solution Approach 2:
The patent extracts the latch-up prevention function from traditional physical structures (guard rings and pick-up structures) and implements it through electrical parameter modification using resistive loads. This removes the need for large-area physical prevention structures while maintaining the protective function.
2Reliability
If shunt path with resistive loads is incorporated to discharge minority carriers, then voltage required to turn on SCR is increased, but circuit complexity increases
Solution Approach 1:
The resistive loads introduced in the patent serve multiple functions: they discharge minority carriers through the shunt path, increase the SCR turn-on voltage, and provide general biasing for the circuit. This multi-functionality reduces overall circuit complexity compared to dedicated latch-up prevention structures.
Solution Approach 2:
The patent combines the latch-up prevention function with the existing circuit biasing network by incorporating resistive loads that serve both as biasing elements and as minority carrier discharge paths. This merging reduces the need for separate prevention circuits and simplifies the overall design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents latch-up in CMOS integrated circuits by increasing the holding voltage required for SCR operation, thus preventing undesired conduction and protecting the circuits from destruction, while reducing the layout area required for latch-up prevention.
Implementation Method 1
Incorporating a shunt path with resistive loads to discharge minority carriers
Implementation Method 2
shunt path with resistive loads to discharge minority carriers, increasing the voltage required to turn on the silicon controlled rectifier (SCR)
Data Source
AI summary
A semiconductor device includes first to fifth regions, first and second resistive loads. The first region is coupled to a first reference voltage terminal. The first to third regions operate as a first transistor. The fourth region is coupled to a second reference voltage terminal. The fourth to fifth regions operate as a second transistor. The first resistive load couples the second region to the second reference voltage terminal. The second resistive load couples the fifth region to the first reference voltage terminal. The first, third, second, fifth and fourth regions are arranged in order, each of the first, second and third regions corresponds to a first conductive type, and each of the fourth and fifth regions corresponds to a second conductive type.