CMOS Layout with High-Resistivity Substrate for RF Switch Insertion Loss
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Solution Overview
Problem
The BiCMOS process used for configuring transmitters and receivers as a single chip results in higher switching loss compared to the SOI process, affecting the receiving performance and output power of RF switches, necessitating a structure that reduces switching loss.
Innovation Solution
A CMOS device with a high-resistivity substrate separating two CMOS structures, each with a triple well structure, is used to reduce interference and signal leakage between the transistors, thereby minimizing switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If BiCMOS process is used to configure transmitter and receiver as a single chip, then integration is achieved, but switching loss increases
Solution Approach 1:
The substrate is divided into multiple high-resistivity regions that are spatially separated, with each region hosting specific CMOS structures. This segmentation isolates signal paths and reduces cross-talk between transmitter and receiver components, thereby reducing switching loss while maintaining single-chip integration.
Solution Approach 2:
Different regions of the substrate are assigned different resistivity characteristics - high-resistivity regions are specifically used for RF switch and LNA areas to minimize signal leakage, while other regions may have different properties optimized for their specific functions. This local differentiation reduces switching loss in critical areas without compromising overall integration.
2Reliability
If high-resistivity substrate is used to separate CMOS structures, then signal leakage is reduced, but device complexity increases
Solution Approach 1:
Multiple high-resistivity regions are merged into a single continuous high-resistivity substrate layer that provides comprehensive signal isolation throughout the device. This unified approach achieves effective signal leakage prevention without requiring separate isolation structures between each CMOS component, thereby reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively reduces interference and signal leakage between transistors, improving insertion loss characteristics and enhancing the performance of RF switches in front-end integrated circuits.
Implementation Method 1
The high-resistivity substrate may have a resistivity value greater than both a resistivity value of the first low-resistivity layer and a resistivity value of the second low-resistivity layer
Data Source
AI summary
A complementary metal oxide semiconductor (CMOS) device includes a high-resistivity substrate; a first CMOS structure disposed in a first region of the high-resistivity substrate; and a second CMOS structure of a same semiconductor type as the first CMOS structure and disposed in a second region of the high-resistivity substrate spaced apart from the first region. The high-resistivity substrate is disposed between the first CMOS structure and the second CMOS structure to separate the first CMOS structure from the second CMOS structure.