CMOS Transistor LDD Fabrication via Segmented Annealing
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Solution Overview
Problem
The challenge in fabricating metal-oxide-semiconductor (MOS) and complementary metal-oxide-semiconductor (CMOS) transistors lies in producing lightly doped drain (LDD) structures for devices of different dimensions, as inappropriate diffusion regions can lead to short channel effects, punch through problems, and degradation of electrical properties, particularly due to varying sizes of I/O and core transistors on the same chip.
Innovation Solution
A method involving the formation of first and second gate structures of different dimensions, followed by the creation of lightly doped drain regions and spacers, and subsequent annealing processes using plasma, laser, or rapid thermal processing to control diffusion, ensuring precise formation of source/drain regions and preventing excessive lateral diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single annealing process is used for LDD structures of different device sizes, then the process is simple and efficient, but the diffusion regions become either too large or too small leading to short channel effect or punch through problems
Solution Approach 1:
The patent divides the annealing process into two distinct stages: a first annealing process performed before spacer formation, and a second annealing process performed after spacer formation. This segmentation allows different diffusion conditions to be applied to different device regions, enabling precise control of LDD diffusion regions for both large and small devices without compromising process efficiency
Solution Approach 2:
The first annealing process is performed as a preliminary action before spacer formation to establish initial LDD diffusion regions. Subsequently, spacers are formed to protect certain areas, and the second annealing process completes the diffusion control. This preliminary action approach enables staged control of diffusion regions for devices of different sizes
2Length of moving object
If the channel length is reduced to scale down transistor size, then device density increases, but short channel effect and hot carrier effect are intensified making device operation difficult
Solution Approach 1:
The patent creates LDD structures with different doping concentrations and diffusion depths in different local regions. Specifically, the first and second LDD diffusion regions have different characteristics tailored to local device size requirements, allowing the channel to maintain proper electric field distribution even when scaled down, thus preventing short channel effects while preserving high device density
3Manufacturing precision
If LDD diffusion regions are made too large for small devices, then lateral diffusion is sufficient, but short channel effect and punch through problems occur
Solution Approach 1:
The patent introduces spacers as intermediary structures formed between the two annealing processes. These spacers act as physical barriers that control the extent of lateral diffusion in the second annealing process, preventing excessive diffusion in small devices while still allowing adequate diffusion in larger devices, thus maintaining proper LDD region dimensions for each device type
4Reliability
If LDD diffusion regions are made too small for large devices, then lateral diffusion is controlled, but high impedance occurs at the overlapping region between LDD and gate, lowering saturated drain current
Solution Approach 1:
The patent employs a dynamic, two-stage annealing approach where the diffusion conditions are adjusted in sequence. The first annealing process provides initial diffusion, and the second annealing process, performed after spacer formation, allows additional controlled diffusion. This dynamic approach ensures that large devices receive sufficient total diffusion to avoid high impedance, while small devices are protected by spacers to prevent over-diffusion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively avoids the formation of too large or too small diffusion regions, mitigating short channel effects and high impedance issues, thereby enhancing the electrical performance and reliability of transistors across different device sizes.
Implementation Method 1
a lightly doped drain annealing process is performed... a source/drain annealing process is performed
Implementation Method 2
The method includes forming a first gate structure and a second gate structure on a substrate... a lightly doped drain annealing process is performed
Data Source
AI summary
A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.