CMOS Device Leakage Current Reduction via Local Ion Concentration

Solution Overview

Problem

CMOS devices experience high leakage current due to the hump phenomenon, which causes different threshold voltages in tapered and flat regions of the poly-Si layer, leading to adverse effects on device quality and operation, especially as devices shrink in size.

Innovation Solution

The solution involves a specific ion implantation process with varying concentrations in different regions of the poly-Si layer, using a half-tone mask and multiple photoresist layers to control the ion distribution, ensuring higher ion concentration in the tapered region of the n-channel MOS and maintaining it unchanged in the p-channel MOS, thereby reducing leakage current without additional photo processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If ion concentration is increased in the tapered region of poly-Si layer to control threshold voltage, then threshold voltage control is improved, but leakage current increases due to hump phenomenon

Engineering Contradiction:
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies different ion concentrations to different regions of the poly-Si layer. Specifically, the tapered region receives a first ion concentration while the flat region receives a second ion concentration, creating local quality differences that control threshold voltage appropriately in each region while preventing the hump phenomenon that causes leakage current.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the poly-Si layer into distinct regions (tapered region and flat region) with different ion concentrations. This segmentation allows independent optimization of threshold voltage control in each region, preventing the uniform ion distribution that leads to the hump phenomenon and associated leakage current.

Inventive Principle:
Principle #1Segmentation

2Object-generated harmful factors

If additional photo process is added to control ion concentration distribution, then leakage current is reduced, but manufacturing cost increases

Engineering Contradiction:
Core Design Contradiction:
Object-generated harmful factorsVSEase of manufacture

Solution Approach 1:

The patent performs ion implantation at different stages of the manufacturing process to achieve the desired ion concentration distribution. By conducting ion implantation before certain manufacturing steps and using selective masking techniques, the patent establishes the correct ion distribution early in the process, eliminating the need for additional photo processes that would increase manufacturing cost.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces leakage current by optimizing ion concentrations across the semiconductor layers, eliminating the hump phenomenon and improving the operational quality of CMOS devices without increasing manufacturing costs.

Implementation Method 1

a first ion implantation is carried out by implanting boron ions B+ into the poly-Si layer 22

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS10026654B2CMOS device with decreased leakage current and method making same
Publication Date: 2018.07.17
  • US10026654B2 patent drawing
  • US10026654B2 patent drawing
  • US10026654B2 patent drawing

AI summary

A method for making a CMOS device includes: providing a substrate with a semiconductor layer and a photoresist layer; irradiating the photoresist layer through a mask to obtain a first photoresist and a second photoresist having a height smaller than that of the first photoresist; first implanting ions to the semiconductor layer; ashing the first and second photoresists to expose a first region of the semiconductor layer and removing the second photoresist to expose a second region of the semiconductor layer; secondly implanting ions to the semiconductor layer; removing the first photoresist to expose a third region of the semiconductor layer surrounded by the second region; forming a third photoresist and a fourth photoresist on the semiconductor layer; etching the semiconductor layer to remove the semiconductor layer not covered by the third and fourth photoresists; removing the third and fourth photoresists; and thirdly implanting ions to the semiconductor layer.