CMOS Sleep Mode Leakage Control via Temperature-Adaptive Voltage
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Solution Overview
Problem
Digital CMOS circuits face challenges in reducing leakage current during sleep mode, where existing solutions fail to efficiently manage voltage drops and temperature effects, leading to suboptimal power consumption and data retention.
Innovation Solution
A circuit with NMOS and PMOS field-effect transistors, integrated on a semiconductor chip, utilizing load devices and an evaluation circuit with analog-to-digital converters and microcontroller cores to adjust voltage drops across load devices based on source voltages and temperature, minimizing leakage current through control loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the supply voltage is maintained in sleep mode, then data retention is ensured, but leakage current increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the supply voltage level in sleep mode based on temperature conditions. At elevated temperatures, the supply voltage is reduced or completely switched off, while at lower temperatures, a reduced voltage level is maintained to preserve data retention. This parameter adaptation resolves the contradiction by optimizing the balance between data retention and leakage current reduction according to actual operating conditions.
Solution Approach 2:
The invention implements dynamics through a control circuit that continuously monitors temperature and dynamically adjusts the supply voltage state accordingly. The system transitions between different operational states (full voltage, reduced voltage, or complete shutdown) based on real-time temperature feedback, enabling adaptive power management that minimizes leakage current while maintaining data integrity when necessary.
2Loss of energy
If the supply voltage is reduced in sleep mode, then leakage current decreases, but data retention capability deteriorates
Solution Approach 1:
The patent resolves this contradiction through parameter changes by establishing temperature-dependent voltage adjustment rules. When temperature exceeds a predetermined threshold, the supply voltage is reduced or switched off to minimize leakage current. When temperature remains below the threshold, a reduced but sufficient voltage level is maintained to ensure data retention. This conditional parameter adjustment optimizes both energy efficiency and reliability.
Solution Approach 2:
The invention employs feedback mechanisms where temperature sensors continuously monitor the operating conditions and provide feedback to the control circuit. Based on this feedback, the control circuit makes informed decisions about supply voltage adjustment, ensuring that leakage current is minimized only when temperature conditions permit, thereby maintaining data retention capability when necessary.
3Productivity
If temperature increases, then leakage current increases, but circuit performance may improve
Solution Approach 1:
The patent addresses this contradiction through parameter changes by implementing temperature-compensated voltage adjustment. When temperature increases, the system responds by reducing or switching off the supply voltage to counteract the increase in leakage current. The control circuit monitors temperature and dynamically adjusts the voltage parameter to maintain optimal operating conditions, preventing excessive power consumption while preserving circuit functionality when appropriate.
Data Source
AI summary
A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.