CMOS I/O Level Shifting With Floating Bias for Low-Power Compatibility
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Solution Overview
Problem
Modern CMOS integrated circuits face challenges in compatibility with older signaling technologies due to voltage level incompatibilities and high power consumption when using DC coupling, particularly in interconnecting with ECL, PECL, and CML interfaces.
Innovation Solution
Implementing a low-power DC coupling technique that utilizes deep N-wells and retrograde P-wells, along with switching voltage regulators, to generate floating voltage biases for level shifting circuits, allowing compatibility with disparate voltage levels while minimizing power consumption by combining the efficiency of AC and DC coupling methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If DC coupling is used to interface modern CMOS circuits with older signaling technologies, then voltage level compatibility is improved, but power consumption increases significantly
Solution Approach 1:
The patent changes the voltage level parameters dynamically by detecting the voltage level of the external signaling technology and configuring the output driver accordingly. The output driver can operate in multiple modes (high voltage mode for ECL/PECL, low voltage mode for CML/LVDS) to match the external device requirements, thereby achieving voltage level compatibility without the continuous high power consumption of traditional DC coupling.
Solution Approach 2:
The patent introduces dynamic control mechanisms including voltage level detection circuits and mode selection logic that adapt the output driver behavior based on the connected signaling technology. This dynamic adaptation allows the system to switch between different operating modes (AC-coupled high voltage mode, DC-coupled high voltage mode, DC-coupled low voltage mode) to optimize both compatibility and power consumption.
2Adaptability or versatility
If high DC voltage levels are used for compatibility with older signaling technologies, then voltage level compatibility is improved, but the risk of exceeding maximum working voltage increases
Solution Approach 1:
The patent implements parameter changes by detecting the voltage level of the external device and adjusting the output driver parameters accordingly. When high voltage compatibility is needed, the system activates high voltage mode with appropriate voltage division ratios. When low voltage external devices are detected, the system switches to low voltage mode, preventing over-voltage conditions and protecting the CMOS circuitry.
Solution Approach 2:
The patent introduces voltage detection circuits and control logic as intermediary elements between the CMOS output driver and the external signaling technology. These intermediaries detect the external voltage level and mediate the connection by selecting appropriate operating modes, thereby preventing direct exposure of sensitive CMOS circuits to incompatible voltage levels.
3Use of energy by moving object
If AC coupling is used to interface with older signaling technologies, then power consumption is reduced, but compatibility with DC-coupled interfaces becomes difficult
Solution Approach 1:
The patent implements multi-functionality by designing the output driver to support multiple coupling modes (AC-coupled high voltage mode and DC-coupled high voltage mode) and multiple voltage levels (high voltage mode for ECL/PECL and low voltage mode for CML/LVDS). This universal design allows a single interface circuit to accommodate various signaling technologies and coupling preferences without requiring separate dedicated circuits for each mode.
Data Source
AI summary
Apparatus and methods efficiently provide compatibility between CMOS integrated circuits and voltage levels that are different from that typically used by modern integrated circuits. For example, backwards compatibility can be desirable. Older signaling interfaces operate at different voltage levels than modern CMOS integrated circuits and conventional circuits to interface with these other signaling interfaces exhibit relatively high power consumption. In the context of a transmitter with a P-type substrate, an output driver is embodied in a deep N-well with retrograde P-wells and is biased with voltage biases that can float with respect to the VDD and VSS supplies provided to the CMOS integrated circuit. In the context of a receiver with a P-type substrate, a portion of a receiver is embodied in a deep N-well and biased with floating voltage biases such that the receiver is compatible with signaling received from a signaling technology with disparate voltage levels.