CMOS Line Driver Calibration for Stable Multi-Wire Bus Impedance
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Solution Overview
Problem
Existing serial communications links face challenges in achieving high pin efficiency, low power consumption, and resilience to noise and crosstalk while maintaining constant output impedance over process variation, voltage, and temperature (PVT) in multi-wire bus systems.
Innovation Solution
A fully-CMOS line driver with calibrated supply voltages is used to match the output impedance to the transmission line and termination impedance, employing a parallel slice architecture for continuous calibration, reducing power consumption and capacitive loading, and utilizing orthogonal differential vector signaling codes like ENRZ and 5b6w to encode information efficiently across multiple wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional line drivers are used in multi-wire bus systems, then communication can be established, but output impedance varies with process, voltage, and temperature (PVT) conditions leading to signal integrity issues
Solution Approach 1:
The patent implements a feedback mechanism where the line driver continuously monitors its output impedance and adjusts its operating parameters to maintain a constant 50-ohm impedance match across PVT variations. This feedback control ensures signal integrity is maintained despite environmental changes.
Solution Approach 2:
The line driver dynamically changes its internal parameters (such as bias currents and transistor operating points) to compensate for PVT variations. By adjusting these parameters in real-time, the driver maintains constant output impedance and optimal signal transmission characteristics.
2Productivity
If traditional serial communication protocols are used, then data can be transmitted, but pin efficiency is low and power consumption is high
Solution Approach 1:
The patent transitions from traditional single-wire or differential-pair serial communication to multi-wire parallel communication, adding spatial dimension to data transmission. This allows multiple bits to be transmitted simultaneously across multiple wires, dramatically improving pin efficiency and reducing the total number of pins required for high-speed communication.
Solution Approach 2:
The communication interface is segmented into multiple independent wire channels, each capable of carrying signal information. This segmentation allows parallel transmission of multiple data streams, increasing overall bandwidth and pin efficiency while distributing power consumption across multiple channels.
3Speed
If high-speed signaling is implemented to increase bandwidth, then data transmission rate improves, but noise resilience and crosstalk increase
Solution Approach 1:
The patent employs differential signaling where signal wires are paired with complement wires, and the receiver detects the voltage difference between paired wires rather than absolute voltages. This equipotential approach with respect to common-mode noise cancels out electromagnetic interference and crosstalk affecting both wires equally, maintaining signal integrity at high speeds.
Solution Approach 2:
The signaling scheme uses asymmetric voltage levels and encoding schemes optimized for the multi-wire configuration. By assigning specific voltage levels and transition patterns to different wire pairs, the system maximizes signal-to-noise ratio and minimizes crosstalk between adjacent wires while maintaining high transmission rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low-power, high-efficiency communication with reduced noise resilience and crosstalk, maintaining constant output impedance across PVT variations, thus improving pin efficiency and reducing power consumption in multi-wire bus systems.
Implementation Method 1
A fully-CMOS line driver with calibrated supply voltages is used to match the output impedance to the transmission line and termination impedance
Implementation Method 2
A low-side on-resistance calibration circuit is configured to generate the first supply voltage based on a voltage drop associated with a replica low-side FET circuit relative to a first voltage drop across a first replica termination impedance element
Data Source
AI summary
Methods and systems are described for an output driver composed of complementary metal-oxide semiconductor (CMOS) devices, the output driver having a line driver control stage configured to selectively output a reference voltage or a first supply voltage at the control stage output node in response to a data signal, and a line driver output circuit configured to generate an output signal on a multi-wire bus, wherein the CMOS devices of the line driver output circuit are calibrated to have an on-resistance matched to a termination impedance via first and second supply voltages provided to the line driver control stage and the line driver output circuit, respectively.