CMOS LNA Output Switching for Split-Port Isolation and Low Noise
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Solution Overview
Problem
Conventional high-frequency low noise amplifiers (LNAs) face challenges in achieving optimal isolation between output ports in split output modes and maintaining low noise figures across various frequency bands, particularly in cellular phone applications.
Innovation Solution
The semiconductor device incorporates three transistors, five switches, two inductors, and a capacitor, with specific switch configurations and inductor-resonator circuits to enhance isolation and noise performance, allowing for both single and split output modes while maintaining low noise figures and high gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiGe bipolar process is used for high-frequency LNA, then low noise performance is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent changes the material parameter from SiGe bipolar to CMOS process, achieving similar low noise performance through different material and process parameters. The CMOS process uses standard semiconductor materials with different electrical characteristics to achieve the same functional goal of low noise amplification at high frequencies
Solution Approach 2:
The patent substitutes the SiGe bipolar process with a CMOS process, replacing a specialized mechanical/fabrication system with a more standardized semiconductor manufacturing process. This substitution maintains the electrical performance while reducing manufacturing complexity and cost
2Adaptability or versatility
If high-frequency switches are incorporated in LNA, then functional versatility is improved, but isolation between output ports deteriorates
Solution Approach 1:
The patent introduces an intermediary circuit configuration with specific switch arrangements (switches 111-114, 121-124) and resonant circuits that mediate between the high-frequency signal paths. These intermediary elements provide the necessary isolation between output ports while allowing the high-frequency switches to maintain their functional versatility in the LNA circuit
3Adaptability or versatility
If split output mode is implemented, then signal distribution capability is improved, but noise performance deteriorates
Solution Approach 1:
The patent segments the output circuit into multiple independent paths with dedicated switches (111-114, 121-124) and resonant circuits for each output port. This segmentation allows the split output mode to distribute signals effectively while maintaining low noise performance through proper isolation and matching in each segmented path
Solution Approach 2:
The patent implements dynamic switching capabilities that allow the LNA to operate in different modes (single output or split output) by controlling the state of switches 111-114 and 121-124. This dynamic reconfiguration maintains optimal noise performance across different operating modes by adjusting the circuit topology according to the required output configuration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves isolation between output ports in split output modes and maintains excellent noise performance across the desired frequency bands, ensuring high gain and low noise figures, thus addressing the limitations of conventional LNAs.
Implementation Method 1
two inductors, and a capacitor... A first inductor and a second inductor each has one terminal connected in series with another terminal of the third switch and which are connected in parallel
Implementation Method 2
A first transistor has a gate into which a high-frequency signal is inputted... a signal amplified with low noise is outputted
Data Source
AI summary
A semiconductor device includes three transistors, five switches, two inductors, and a capacitor. A first transistor has a gate. The switches have one terminal connected in series with a drain of the first transistor in parallel. A second transistor has a source connected to the first switch and a grounded gate. A third transistor having a source connected to the second switch and a grounded gate. A first inductor and a second inductor each has one terminal connected in series with the third switch in parallel. A fourth switch has one terminal connected to the first inductor and another terminal connected to the source of the second transistor. A fifth switch has one terminal connected to the second inductor and another terminal connected to the source of the third transistor. A capacitor connected between the one terminal of the fourth switch and the one terminal of the fifth switch.