CMOS Gate and Source-Drain Mask Reduction
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Solution Overview
Problem
The existing CMOS production processes require multiple mask steps for forming gate electrodes and source/drain regions, leading to increased process complexity and cost.
Innovation Solution
A method where the well and source/drain regions are formed using the same resist mask, with additional ion implantations to create a pocket implantation region, reducing the number of mask steps by performing these operations simultaneously with the gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate mask steps are used for forming gate electrodes and source/drain regions, then the formation of each structure can be precisely controlled, but the number of mask steps increases to four
Solution Approach 1:
The patent combines the formation of gate electrodes and source/drain regions into a single mask step. A resist mask is formed with openings that simultaneously define both the gate electrode regions and the source/drain regions. Ion implantation is then performed in one step to form both structures, eliminating the need for separate mask steps while maintaining precise control over the dimensions and positions of both features.
2Manufacturing precision
If multiple mask steps are used for forming gate electrodes and source/drain regions, then each structure can be independently optimized, but the production process becomes more complex and costly
Solution Approach 1:
The patent merges the mask formation steps for gate electrodes and source/drain regions into a single resist patterning operation. The resist mask is designed with opening patterns that simultaneously define both structures. This single mask step approach reduces the number of photolithography and etching operations, thereby simplifying the manufacturing process and reducing costs while still allowing independent optimization of the gate and source/drain structures through careful mask design.
Solution Approach 2:
The resist mask serves multiple functions simultaneously: it defines the gate electrode regions, defines the source/drain regions, and acts as a mask for the ion implantation process that forms both structures. This multi-functional approach eliminates the need for separate masks for each structure, reducing process complexity while maintaining the ability to independently optimize each structure's dimensions and positions.
3Device complexity
If the same resist mask is used for forming both gate electrodes and source/drain regions, then the number of mask steps is reduced to three, but the timing of ion implantation must be carefully controlled
Solution Approach 1:
The patent performs preliminary actions by forming the resist mask with openings that pre-define both the gate electrode regions and source/drain regions before ion implantation. The mask is designed in advance to accommodate both structures, and the ion implantation parameters (energy, dose, angle) are predetermined to achieve the desired doping profiles for both gate and source/drain regions in a single step, reducing the need for complex timing control during the actual implantation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of mask steps from four to three, lowering process costs and simplifying the CMOS production process while enabling the formation of transistors with LDD structures.
Implementation Method 1
forming a first conductivity type or second conductivity type well in an active region separated by the element isolation film; forming a source region and a drain region having a conductivity type opposite to the conductivity type of the well, in a part of a surface of the substrate in each active region; the step of forming the well and at least part of the step of forming the source region and the drain region are performed by ion implantations
Data Source
AI summary
The invention provides a method for producing a semiconductor device that can reduce the number of mask steps. In a CMOS production process, gate electrodes are formed in regions for forming an NMOS and a PMOS at the same time with a common mask pattern, and after the gate electrodes have been formed, a well, and source and drain regions are formed by impurity ion implantations with a common mask pattern in each region of the NMOS and the PMOS, using the gate electrode as a mask, whereby the number of mask steps is reduced.