CMOS Fabrication Mask Reduction via Disposable Spacer Trimming
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Solution Overview
Problem
The complexity and high cost of CMOS integrated circuit fabrication processes due to the need for multiple masks in traditional methods, which results in low manufacturing efficiency and increased time consumption.
Innovation Solution
A process that reduces the number of masks required by patterning gates in NMOS and pMOS regions using fewer masks, employing disposable spacers to trim and etch back, and conducting doping steps with selective masking to achieve CMOS transistor formation with six or fewer masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional multiple masking steps are used to define CMOS transistors, then manufacturing precision is maintained, but device complexity and manufacturing time increase significantly
Solution Approach 1:
The patent combines multiple masking operations into a single masking step. Specifically, it uses one mask to simultaneously define the active areas for both NMOS and pMOS transistors, as well as the gate regions, eliminating the need for separate masks for each transistor type and each fabrication stage. This merging of operations maintains precision while dramatically reducing process complexity.
Solution Approach 2:
The single mask used in the invention serves multiple functions: it defines the active areas for NMOS transistors, defines the active areas for pMOS transistors, and defines the gate regions for both transistor types. This multi-functional mask replaces what traditionally required four or more separate masks, reducing complexity while maintaining the precision needed for each specific definition task.
2Manufacturing precision
If multiple masking steps are employed for CMOS fabrication, then doping precision is achieved, but loss of time and low productivity result
Solution Approach 1:
The patent merges multiple doping operations that traditionally required separate masking steps into a single doping operation. By using one mask to define all necessary regions (NMOS active areas, pMOS active areas, and gate regions), the invention enables simultaneous doping of all these regions in one step, maintaining doping precision while eliminating the time loss associated with multiple sequential masking and doping cycles.
Solution Approach 2:
The invention enables continuous doping action across all transistor regions in a single operation. Instead of interrupting the process with multiple masking steps, the single mask allows the doping process to proceed continuously across NMOS and pMOS regions simultaneously, maximizing productivity while maintaining the precision required for each doping zone.
3Reliability
If traditional CMOS fabrication processes are used, then transistor performance is maintained, but the number of masks and process steps increases cost and time
Solution Approach 1:
The patent combines multiple fabrication operations into a single integrated process step. By using one mask to define all critical regions (active areas and gates for both NMOS and pMOS transistors) and performing doping in one operation, the invention maintains transistor performance requirements while reducing fabrication time by eliminating the sequential steps and waiting periods associated with traditional multi-mask processes.
Data Source
AI summary
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the NMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.