Super-Flat CMOS Memory Interface via Dummy Via Segmentation
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Solution Overview
Problem
The integration of CMOS metal layers and memory junction layers in non-volatile memory fabrication is hindered by the need for a super-flat under-layer surface, which is difficult to achieve due to wafer warpage and local flatness deterioration, especially with the addition of back-end metal layers, and the challenge of planarizing Cu CMP processes across varying metal layouts.
Innovation Solution
A method is introduced that splits the formation of active and dummy vias into two different mask patterning steps, with dummy vias stopping at an etch-stop layer and active vias penetrating it to create a super-flat interface between the CMOS and device levels, using a double pattern process to form a uniform array of active and dummy devices on uniformly patterned buffer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple back-end metal layers are built on a wafer, then the functionality and integration density of the memory device is improved, but the global and local wafer flatness and warpage deteriorate significantly due to built-in stress and process variations
Solution Approach 1:
The patent segments the via formation process into two distinct patterning steps: first forming dummy vias that stop at the etch-stop layer, then forming active vias that penetrate through it. This segmentation allows independent optimization of each via type, enabling the dummy vias to compensate for warpage and maintain local flatness while accommodating multiple metal layers for high integration density.
Solution Approach 2:
The patent applies different via structures at different locations: dummy vias are formed in regions where only local planarization is needed, while active vias are formed where electrical connection is required. This local differentiation allows the dummy vias to specifically address the wafer flatness problem in critical areas without compromising the overall integration density achieved through multiple metal layers.
2Manufacturing precision
If Cu CMP processes are used for back end of line processes, then the metal layers are planarized, but it is difficult to planarize across the wafer surface due to varying metal layouts with many Cu lines and vias
Solution Approach 1:
The patent performs preliminary action by forming dummy vias before the Cu CMP process. These dummy vias are strategically placed to pre-compensate for areas that will undergo significant planarization, ensuring that the subsequent CMP process can achieve uniform flatness across the wafer surface even with complex metal layouts containing many Cu lines and vias.
Solution Approach 2:
The dummy vias act as intermediaries between the complex metal layout and the CMP process. They provide a uniform structural baseline that facilitates the CMP planarization process, allowing the removal of excess copper while maintaining consistent surface flatness across regions with varying metal density and pattern complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances interfacial flatness and relaxes pattern size constraints, improving CD control and preventing peeling of buffer layers during annealing, resulting in a stable and smooth surface for memory junction layer formation.
Implementation Method 1
splits the formation of active and dummy vias into two different mask patterning steps, with dummy vias stopping at an etch-stop layer
Implementation Method 2
The back end of line processes normally consist of Cu CMP (chemical mechanical polishing) processes
Implementation Method 3
The buffer layers are for the purpose of preventing diffusion of Cu into the device level
Implementation Method 4
preventing peeling of buffer layers during annealing
Data Source
AI summary
The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.