CMOS-MEMS Integration via Through-Chip Vias

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Solution Overview

Problem

The traditional methods for integrating microelectromechanical system (MEMS) devices with complementary metal-oxide semiconductor (CMOS) devices through wire bonding are costly and result in waste of device areas due to the need to remove parts of the MEMS and cap wafers to expose bonding pads, and the process of creating through-silicon vias (TSVs) is challenging, especially with thick cap wafers, making it difficult to control the taper profile and deposition of isolation and metal layers.

Innovation Solution

The integration of CMOS-MEMS devices using a through-chip via process with improved TSV structures, where vias pass through the cap wafer, allowing for eutectic bonding and conductive connections between CMOS and MEMS structures without the need for extensive wafer removal, utilizing techniques like deep reactive ion etching and conductive routing layers to establish connections efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wire bonding is used to connect MEMS and CMOS devices, then electrical connections are established, but fabrication costs increase and device area is wasted due to wafer removal

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidfabrication cost and complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the MEMS device and CMOS device onto a single substrate, eliminating the need for separate wire bonding processes. The conductive vias are formed through the substrate to directly connect the MEMS device to the CMOS device, combining what were previously separate components requiring external interconnection.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces conductive vias as an intermediary structure formed through the substrate to establish electrical connections between the MEMS device and CMOS device. This mediator eliminates the need for wire bonding by providing a direct conductive path through the substrate, reducing both cost and complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If parts of MEMS and cap wafers are removed to expose bonding pads, then wire bonding can be performed, but device area is wasted

Engineering Contradiction:

Improvebonding pad accessibilityVSAvoiddevice area utilization

Core Design Contradiction:

Ease of operationVSArea of stationary object

Solution Approach 1:

The patent transitions from surface-level bonding pad exposure to three-dimensional through-substrate via formation. Instead of removing material from the wafer surface to expose pads, conductive vias are formed vertically through the substrate, allowing connections without sacrificing surface area for pad exposure.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If through-silicon vias are created with thick cap wafers, then direct connections are achieved, but control over taper profile and deposition becomes difficult

Engineering Contradiction:

Improvevia formation precisionVSAvoidprocess control complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming the conductive vias through the substrate before finalizing the CMOS device fabrication. This early via formation allows subsequent deposition processes to be optimized and controlled more effectively, as the via structures are already in place to guide material deposition.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameters of the via formation process by using specific etching techniques and deposition conditions that enable precise control of the taper profile even in thick cap wafers. By adjusting etch selectivity, deposition temperature, and material composition, the process achieves both precision and controllability.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces fabrication costs, minimizes waste, and enhances the control over the taper profile and deposition processes, enabling reliable and efficient electrical connections between CMOS and MEMS devices, improving the integration process.

Implementation Method 1

utilizing techniques like deep reactive ion etching and conductive routing layers to establish connections efficiently

Methodology Applied

Scientific EffectDeep reactive ion etching:

Implementation Method 2

allowing for eutectic bonding and conductive connections between CMOS and MEMS structures

Methodology Applied

Scientific EffectEutectic bonding:

Data Source

PatentUS11235969B2CMOS-MEMS integration with through-chip via process

Publication Date: 2022.02.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The integrated CMOS-MEMS device includes a CMOS structure, a cap structure, and a MEMS structure. The CMOS structure, fabricated on a first substrate, includes at least one conducting layer. The cap structure, including vias passing through the cap structure, has an isolation layer deposited on its first side and has a conductive routing layer deposited on its second side. The MEMS structure is deposited between the first substrate and the cap structure. The integrated CMOS-MEMS device also includes a conductive connector that passes through one of the vias and through an opening in the isolation layer on the cap structure. The conductive connector conductively connects a conductive path in the conductive routing layer on the cap structure with the at least one conducting layer of the CMOS structure.