CMOS Mesa Structure for Crystallographic Orientation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current CMOS devices face challenges in achieving enhanced performance by fabricating complementary p-FET and n-FET transistors with different semiconductor substrate channel crystallographic orientations on a single substrate, while maintaining low energy consumption and ease of fabrication.

Innovation Solution

The solution involves creating semiconductor structures with pairs of mesas within a substrate, where each mesa has a specific ratio of channel effective horizontal to vertical surface area, allowing transistors to benefit from optimized crystallographic orientations, with one mesa having a vertical orientation and the other a horizontal orientation, and using these orientations to enhance transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different crystallographic orientations are used for p-FET and n-FET channels, then charge carrier mobility and transistor performance are improved, but device complexity and fabrication difficulty increase

Engineering Contradiction:
Improvetransistor performanceVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The semiconductor substrate is divided into multiple regions, each with different crystallographic orientations (e.g., <100> for n-FETs and <110> for p-FETs). This segmentation allows each transistor type to benefit from its optimal orientation while maintaining a single substrate structure, resolving the contradiction between performance improvement and device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different local regions of the substrate are assigned different crystallographic orientations tailored to specific transistor types. The <100> orientation is localized to n-FET channel regions while <110> orientation is localized to p-FET channel regions, enabling locally optimized performance without requiring the entire device to be complex.

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple crystallographic orientations are integrated on a single substrate, then individually optimized performance of p-FETs and n-FETs is achieved, but manufacturing complexity increases

Engineering Contradiction:
Improveindividually optimized performanceVSAvoidease of manufacture
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The substrate is segmented into distinct orientation domains that can be fabricated using standard CMOS processes. By dividing the substrate into <100> and <110> regions, the patent enables individually optimized transistor performance while maintaining compatibility with existing manufacturing techniques, thus improving ease of manufacture compared to requiring entirely new fabrication approaches.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A single semiconductor substrate performs multiple functions by accommodating different crystallographic orientations for different transistor types. The substrate simultaneously supports n-FETs with <100> orientation and p-FETs with <110> orientation, eliminating the need for separate substrates or specialized fabrication processes and thereby improving ease of manufacture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If vertical crystallographic orientation is used for one device and horizontal for another, then charge carrier mobility is enhanced for each device type, but fabrication process complexity increases

Engineering Contradiction:
Improvecharge carrier mobilityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The channel regions are segmented into vertical and horizontal crystallographic orientations based on device type. Vertical orientation (<110>) is assigned to p-FET channels while horizontal orientation (<100>) is assigned to n-FET channels, enabling enhanced charge carrier mobility for each device type while using standard segmentation techniques that do not significantly increase fabrication process complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7785955B2CMOS structure and method including multiple crystallographic planes
Publication Date: 2010.08.31 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US7785955B2 patent drawing
  • US7785955B2 patent drawing
  • US7785955B2 patent drawing

AI summary

A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater than the first ratio. A first device having a first polarity uses the first mesa as a channel and benefits from the enhanced vertical crystallographic orientation. A second device having a second polarity different from the first polarity uses the second mesa as a channel and benefits from the enhanced horizontal crystallographic orientation.