CMOS Metal Gate Fabrication via Segmented Trench Formation
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Solution Overview
Problem
CMOS devices fabricated using the high-K metal gate (HKMG) process face under-expected performance due to increased leakage current, depletion of the gate electrode layer, and mobility degradation, which are not adequately addressed by existing fabrication methods, leading to reduced yield and increased risk of cross-contamination.
Innovation Solution
A method for fabricating CMOS devices involving the formation of trenches with specific barrier layers and work function layers to protect gate regions, allowing for independent formation of metal gates in NMOS and PMOS regions, ensuring accurate material filling and reducing the need for complex multi-layered work function processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-K metal gate (HKMG) process is used to substitute silicon dioxide and polycrystalline silicon, then leakage current and gate electrode layer depletion problems are solved, but device performance is under-expected and cannot match design requirements
Solution Approach 1:
The patent divides the gate formation process into separate sequential steps for NMOS and PMOS regions. First, a first trench is formed on the NMOS active region with a first barrier layer and first work function layer, then a second trench is formed on the PMOS active region with a second barrier layer and second work function layer. This segmentation allows independent optimization of each transistor type's gate structure, resolving the contradiction between reliability improvement and manufacturing precision.
Solution Approach 2:
The patent applies different barrier layers and work function layers to different regions (NMOS vs PMOS) to achieve locally optimized gate characteristics. The first barrier layer and first work function layer are tailored for NMOS, while the second barrier layer and second work function layer are tailored for PMOS, ensuring each region has the specific properties needed for optimal performance rather than using a uniform approach.
2Adaptability or versatility
If conventional HKMG fabrication method is used, then gate dielectric and gate electrode are replaced, but cross-contamination risk increases and yield decreases
Solution Approach 1:
The patent segments the gate formation into distinct sequential steps with separate barrier layers for NMOS and PMOS regions. The first barrier layer protects the NMOS region during first trench formation, and the second barrier layer protects the PMOS region during second trench formation. This segmentation prevents cross-contamination between regions, maintaining high yield while enabling material substitution.
Solution Approach 2:
The patent forms barrier layers and work function layers as preliminary protective structures before forming the metal gates. The first barrier layer is formed before the first trench, and the second barrier layer is formed before the second trench, preventing contamination during subsequent processing steps and ensuring high yield.
3Manufacturing precision
If complex multi-layered work function processes are used, then gate performance can be optimized, but process complexity increases
Solution Approach 1:
The patent segments the work function layer formation into separate steps for NMOS and PMOS regions, with the first work function layer formed in the first trench and the second work function layer formed in the second trench. This segmentation simplifies the overall process by allowing independent formation of work function layers rather than requiring a complex multi-layered approach for both regions simultaneously.
Solution Approach 2:
The patent applies different work function layers locally to NMOS and PMOS regions to achieve optimal gate performance for each transistor type. The first work function layer is optimized for NMOS, and the second work function layer is optimized for PMOS, maintaining high manufacturing precision while avoiding the complexity of uniform multi-layered structures.
Data Source
AI summary
A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes forming a first trench on the first active region using a first barrier layer and a second substitute gate electrode layer to protect a gate region on the second active region, followed by forming a first work function layer and a first metal gate in the first trench. Further, the method includes forming a second trench on the second active region using a second barrier layer to protect the first metal gate structure, followed by forming a second work function layer and a second metal gate in the second trench.