CMOS Microfluidic Channel Structure for Integrated Ion-Sensitive FETs
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Solution Overview
Problem
Existing methods for integrating ion-sensitive field effect transistors (FETs) in chip manufacturing are expensive due to additional wafer processing and bonding, necessitating improved structures and fabrication methods for transistor-based sensors.
Innovation Solution
A semiconductor structure is formed with a monocrystalline first semiconductor layer having a cavity filled with a sacrificial oxide and capped with a polycrystalline second semiconductor layer, featuring a microfluidic channel and ports, using CMOS-compatible processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional wafer bonding and etching processes are used to form microfluidic channels, then the channels can be integrated with FETs, but the manufacturing cost increases due to additional processing steps
Solution Approach 1:
The patent merges the microfluidic channel formation process with the existing CMOS transistor fabrication process. The channel is formed by defining a region during the transistor fabrication sequence itself, eliminating the need for separate wafer bonding and etching steps. This integration maintains reliable FET-channel integration while significantly reducing manufacturing complexity and cost.
Solution Approach 2:
The patent creates a multi-functional structure where the same semiconductor layers and processing steps serve dual purposes: forming both the FET transistor and the microfluidic channel. The channel region is defined using the same dopant layers and oxide structures that are already present in the transistor, making the process universally applicable to standard CMOS fabrication without requiring additional specialized equipment or steps.
2Reliability
If additional wafer processing and bonding steps are added, then FET integration is achieved, but the process complexity and time increase
Solution Approach 1:
The patent performs preliminary actions by pre-defining the channel region during the transistor fabrication process itself. The channel is formed by utilizing the existing oxide and dopant layers that are already deposited and patterned for transistor creation. This preliminary formation of the channel structure eliminates the need for subsequent separate bonding and etching operations, reducing overall process complexity while ensuring reliable FET integration.
3Measurement precision
If conventional sensor fabrication methods are used, then accurate ion detection is achieved, but the manufacturing cost and time increase
Solution Approach 1:
The patent combines ion-sensitive FET fabrication with microfluidic channel formation into a single integrated process. The channel is created within the transistor structure during normal CMOS fabrication, allowing accurate ion detection through the FET while maintaining high manufacturing efficiency. This eliminates the need for separate, time-consuming sensor assembly processes.
Data Source
AI summary
Disclosed is a semiconductor structure including a monocrystalline silicon layer having a first surface and a second surface opposite the first surface. A cavity extends into the first semiconductor layer at the second surface. The structure also includes a polycrystalline silicon layer adjacent to the second surface and extending over the cavity. At least one opening extends through the second semiconductor layer to the cavity.