CMOS Multi-Pinned Pixel Dark Current Reduction
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Solution Overview
Problem
Conventional 5TPPD pixels suffer from high dark current and charge trapping/recombination issues at transfer gates, which obscure low signal levels and reduce charge transfer efficiency, especially when measuring extremely low signal levels.
Innovation Solution
A CMOS multi-pinned pixel architecture is introduced, where a multi-pinned (MP) implant layer is uniformly applied across the 5TPPD pixel, including the pinned-photodiode and transfer gate regions, to create a 'buried channel' that prevents dark current and recombination, while maintaining high charge transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 5TPPD pixel structure is used, then basic photo detection function is achieved, but dark current is high and charge transfer efficiency is reduced due to trapping and recombination at transfer gates
Solution Approach 1:
The patent divides the transfer gate structure into multiple pinned regions (first pinned region and second pinned region) at opposite edges of the photodiode. This segmentation allows each pinned region to independently suppress dark current and trapping effects at its respective transfer gate interface, thereby improving overall charge transfer efficiency while reducing total dark current generation.
Solution Approach 2:
The patent applies pinning layers specifically at the transfer gate interfaces where dark current and trapping effects occur most severely. By concentrating the pinning function at these critical locations rather than uniformly throughout the structure, the patent effectively suppresses harmful effects at the interfaces while maintaining optimal charge collection properties in the bulk photodiode region.
2Measurement precision
If transfer gates are used for charge transfer, then charge collection function is achieved, but trapping and recombination effects reduce measured signal level
Solution Approach 1:
The patent implements pinning layers at the transfer gate interfaces before charge transfer occurs. This preliminary action of pinning the interfaces suppresses trapping and recombination effects in advance, ensuring that when charge is transferred through the gates, minimal signal loss occurs due to trapping or recombination, thereby improving measurement precision.
Solution Approach 2:
The patent converts the potentially harmful interface states at transfer gate Si-SiO2 interfaces into beneficial pinned states. By introducing pinning layers that create fixed charge layers, the patent transforms the interface regions from sources of trapping and recombination into regions that actively suppress these effects, thereby improving charge transfer efficiency and signal measurement accuracy.
3Productivity
If Si-SiO2 interface is present at transfer gates, then charge transfer path is formed, but dark current is generated and signal levels are obscured
Solution Approach 1:
The patent introduces pinning layers as intermediary structures between the silicon and SiO2 at the transfer gate interfaces. These pinning layers act as mediators that maintain the necessary electrical properties for charge transfer while simultaneously suppressing dark current generation at the Si-SiO2 interface, thus preserving charge transfer speed while eliminating harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves ultra-low dark current and near-perfect charge transfer efficiency without trapping or recombination, effectively enhancing the pixel's ability to measure low signal levels by passivating the Si-SiO2 interface and maintaining the pinning function.
Implementation Method 1
passivating the Si-SiO2 interface
Implementation Method 2
pinned-photo diode (PPD) 102 as a photosensitive element for photo generating and collecting electrical charge
Data Source
AI summary
A CMOS multi-pinned pixel having very low dark current and very high charge transfer performance over that of conventional CMOS pixels is disclosed. The CMOS pixel includes epitaxial silicon and at least one transfer gate formed upon the epitaxial silicon. A pinned-photodiode is formed in the epitaxial silicon. A multi-pinned (MP) implant layer is implanted in the epitaxial silicon at least partially extending across the pinned-photodiode and substantially underlying the at least one transfer gate of the CMOS pixel to promote dark current passivation during an accumulation state and promote charge transfer during a transfer state.