CMOS Multiplier Linearization With Feedback and Pre-Distortion
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Solution Overview
Problem
CMOS multipliers suffer from non-linearity due to the non-linear voltage-current transfer function of CMOS differential stages, which affects the overall linearity and accuracy of the multiplier.
Innovation Solution
A highly linear multiplier is designed using a configuration that includes a first transconductance stage with negative feedback, second transconductance stages for pre-distorting input voltages, and third transconductance stages for outputting differential currents, all of which are integrated with a combination network to generate the output current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS transistors are operated in weak inversion to achieve exponential characteristic curve, then the multiplier can be implemented in CMOS technology, but the bandwidth is reduced and accuracy is low due to temperature drift
Solution Approach 1:
The patent introduces feedback networks in the transconductance stages to linearize the voltage-current transfer function. The feedback mechanism compensates for the non-linear characteristics of CMOS differential stages, thereby improving multiplication accuracy without requiring weak inversion operation, thus avoiding temperature drift issues
Solution Approach 2:
The patent changes the operating parameters of CMOS transistors from weak inversion to saturation region operation. By operating in saturation with optimized bias conditions and using feedback linearization, the patent achieves both CMOS compatibility and high accuracy, eliminating the temperature drift problem associated with weak inversion operation
2Measurement precision
If pre-distortion is applied to compensate for non-linearity in bipolar multipliers, then high precision is achieved, but the circuit cannot be directly applied to CMOS technology due to lack of base current
Solution Approach 1:
The patent adapts the pre-distortion concept for CMOS by changing the implementation approach from current-based (bipolar) to voltage-based (CMOS). The second transconductance stages apply pre-distortion to the voltage input signals, compensating for the non-linear voltage-current transfer function of CMOS differential stages, thereby achieving high precision in CMOS multipliers
Solution Approach 2:
The patent introduces intermediate transconductance stages that convert voltage inputs to currents with pre-distorted characteristics. These intermediate stages act as mediators that apply the pre-distortion function in a CMOS-compatible manner, enabling high-precision multiplication without requiring bipolar transistor characteristics
3Ease of manufacture
If standard CMOS differential stage is used, then the circuit is simple and easy to manufacture, but non-linearity in the voltage-current transfer function reduces overall accuracy
Solution Approach 1:
The patent adds feedback networks to the transconductance stages while maintaining the basic CMOS differential stage structure. The feedback paths linearize the voltage-current transfer function without requiring complete redesign of the differential stage, thus preserving ease of manufacture while significantly improving linearity accuracy
Solution Approach 2:
The patent divides the multiplier circuit into multiple transconductance stages, each handling specific functions. The first transconductance stage processes one input voltage, while second transconductance stages process the other input voltage with pre-distortion. This segmentation allows each stage to be optimized for linearity while maintaining overall circuit simplicity and manufacturability
Data Source
AI summary
There is provided a linearized multiplier configured to produce an output current representing a product of a first input voltage and a second input voltage, comprising: a first transconductance stage which is configured to input the first input voltage and to output a first pair of differential currents, wherein the first transconductance stage comprises a negative feedback network, at least one second transconductance stage which is configured to input the second input voltage and to output a pre-distorted voltage of the second input voltage, wherein each second transconductance stage comprises a negative feedback network, a pair of third transconductance stages, each of which is configured to input a voltage corresponding to the pre-distorted voltage of the second input voltage and to output a second pair of differential currents, when being supplied with a bias current corresponding to a respective current of the first pair of differential currents.