CMOS Multiplier Linearization with Feedback-Driven Pre-Distortion
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Solution Overview
Problem
CMOS-based multipliers, particularly Gilbert-type multipliers, face challenges in achieving high accuracy due to non-linearity issues in CMOS differential stages, which affect the overall linearity and accuracy of the multiplier.
Innovation Solution
A multiplier configuration that includes a first transconductance stage with a negative feedback network, paired with second and third transconductance stages also employing negative feedback networks, to linearize the voltage-input units and compensate for non-linearity, utilizing MOSFET transistors in CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a Gilbert-type multiplier is implemented in CMOS technology, then energy efficiency and scalability are improved, but linearity and accuracy deteriorate due to non-linearity in CMOS differential stages
Solution Approach 1:
The patent applies pre-distortion to the input voltages before they are processed by the CMOS differential stages. By预先 modifying the input signals to anticipate and compensate for the known non-linear characteristics of the CMOS stages, the overall multiplication accuracy is improved without requiring changes to the fundamental CMOS architecture, thus maintaining energy efficiency while enhancing linearity.
2Adaptability or versatility
If MOSFETs are operated in weak inversion to achieve exponential characteristic curves, then the Gilbert cell can be realized in CMOS, but bandwidth decreases and temperature drift increases
Solution Approach 1:
The patent operates MOSFETs in the saturation region rather than weak inversion, utilizing the square-law characteristic (I_D proportional to (V_GS - V_TH)^2) instead of exponential behavior. This parameter change in the operating region allows the circuit to achieve the Gilbert cell functionality in CMOS while maintaining higher bandwidth and reduced temperature drift, though it requires different biasing and circuit design approaches.
3Measurement precision
If pre-distortion is applied to compensate for non-linearity in CMOS differential stages, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the output of the multiplication is fed back through additional CMOS differential stages that apply corrective signals. This feedback approach automatically compensates for non-linearities without requiring complex external pre-distortion circuitry, thereby improving accuracy while keeping the overall device complexity manageable through systematic feedback control.
4Ease of manufacture
If standard CMOS differential stages are used, then ease of manufacture is maintained, but non-linearity affects overall multiplier accuracy
Solution Approach 1:
The patent introduces intermediate correction stages using additional CMOS differential stages that process the output signals. These intermediary stages act as mediators that compensate for the non-linearities introduced by the main multiplication stages. By inserting these corrective intermediate stages, the patent maintains compatibility with standard CMOS manufacturing processes while improving the overall accuracy of the multiplier through systematic error correction.
Data Source
AI summary
There is provided a linearized multiplier configured to produce an output current representing a product of a first input voltage and a second input voltage, comprising: a first transconductance stage which is configured to input the first input voltage and to output a first pair of differential currents, wherein the first transconductance stage comprises a negative feedback network, at least one second transconductance stage which is configured to input the second input voltage and to output a pre-distorted voltage of the second input voltage, wherein each second transconductance stage comprises a negative feedback network, a pair of third transconductance stages, each of which is configured to input a voltage corresponding to the pre-distorted voltage of the second input voltage and to output a second pair of differential currents, when being supplied with a bias current corresponding to a respective current of the first pair of differential currents.