CMOS Multi-Well Electrode Array With Wafer-Scale Signal Routing
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Solution Overview
Problem
Existing semiconductor devices for electrical assessment of cells in multiple-well arrays are costly due to complex fabrication procedures and lack efficient integration of circuitry with electrodes, limiting their application in biomedical and other fields.
Innovation Solution
A CMOS-compatible, wafer-scale multi-well platform with integrated circuitry on a silicon wafer, using standard fabrication processes to interface with electrodes, allowing for efficient routing of digital and analog signals and incorporating reconfigurable peripheral circuits for electrical communication with electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard CMOS fabrication processes are used, then production cost is reduced and manufacturing ease is improved, but device complexity and integration capability are limited
Solution Approach 1:
The wafer is divided into multiple reticle areas, each containing multiple wells with electrode arrays and associated circuitry. This segmentation allows standard CMOS fabrication processes to be applied to each module independently while enabling complex multi-well integration at the wafer level, thus reducing per-unit fabrication cost while maintaining overall system complexity through modular architecture.
2Device complexity
If circuitry is integrated on a single large wafer, then signal routing efficiency is improved and device complexity is reduced, but manufacturing precision and fabrication difficulty increase
Solution Approach 1:
The large wafer is segmented into multiple reticle areas, each containing multiple wells with electrode arrays and associated circuitry. This segmentation allows standard CMOS fabrication processes to be applied to each module independently while enabling complex multi-well integration at the wafer level, thus reducing per-unit fabrication cost while maintaining overall system complexity through modular architecture.
Solution Approach 2:
The patent routes signals in multiple directions (first direction across reticle areas, second direction within reticle areas) and uses redistribution layers above and below the wafer to manage signal routing. This multi-dimensional routing approach distributes the routing complexity across different spatial dimensions, making it more manageable while maintaining efficient signal transmission throughout the device.
3Adaptability or versatility
If multiple reticle areas are connected with cross-reticle connections, then adaptability and signal routing flexibility are improved, but device complexity and routing difficulty increase
Solution Approach 1:
The patent routes signals in multiple directions (first direction across reticle areas, second direction within reticle areas) and uses redistribution layers above and below the wafer to manage signal routing. This multi-dimensional routing approach distributes the routing complexity across different spatial dimensions, making it more manageable while maintaining efficient signal transmission throughout the device.
Data Source
AI summary
Disclosed herein are semiconductor devices to provide a CMOS-compatible, wafer-scale, multi-well platform that can be used for biomedical or other applications, and methods to operate the same. In some embodiments, circuitry is provided underneath a multiple-well array to electrically interface with electrodes in the wells. To interface with electrodes in a large array, circuitry may be fabricated on a single silicon (Si) wafer having a dimension that is at least the same or larger than that of the multiple-well array. According to one aspect of the present disclosure, standard CMOS fabrication process such as those known to be used in a standard semiconductor foundry may be used without expensive customization for complex fabrication procedures. This may help the production cost to be lowered in some cases.