Fully CMOS MUX Slices for Low-Power 200G+ Serialization
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Solution Overview
Problem
Existing high-speed serializer designs face challenges in achieving low power consumption and efficient performance due to improper architecture selection, particularly in generating and distributing half-rate clocks, leading to poor power efficiency and performance issues at data rates over 200 gigabits/second.
Innovation Solution
The implementation of a multiplexer system with Q-mux and I-mux slices, incorporating inverters and buffers to balance clock and data signal propagation delays, and a direct interconnection between multiplexers to synchronize data transitions, along with digital-to-analog converters for signal amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a typical single stage multiplexer is used with shared output node, then device complexity is reduced, but power consumption increases due to large self-loading
Solution Approach 1:
The multiplexer is divided into two stages: a first stage with multiple 2-to-1 multiplexers (M21, M22) that select between input pairs, and a second stage with a final multiplexer (M23) that selects between the outputs of the first stage. This segmentation distributes the selection logic across multiple components, reducing the self-loading on any single output node while maintaining the overall multiplexing function.
2Reliability
If quarter-rate architecture is used for MUX implementation, then timing requirements are relaxed, but power efficiency deteriorates due to large self-loading
Solution Approach 1:
The multiplexer is divided into two stages: a first stage with multiple 2-to-1 multiplexers (M21, M22) that select between input pairs, and a second stage with a final multiplexer (M23) that selects between the outputs of the first stage. This segmentation distributes the selection logic across multiple components, reducing the self-loading on any single output node while maintaining the overall multiplexing function.
3Speed
If serializer architecture is optimized for high speed, then data rate increases, but power consumption increases by 60-70%
Solution Approach 1:
The multiplexer is divided into two stages: a first stage with multiple 2-to-1 multiplexers (M21, M22) that select between input pairs, and a second stage with a final multiplexer (M23) that selects between the outputs of the first stage. This segmentation distributes the selection logic across multiple components, reducing the self-loading on any single output node while maintaining the overall multiplexing function.
Solution Approach 2:
The serializer uses quarter-rate clocking where the final multiplexer operates at one-quarter the data rate, selecting between four input pairs over four clock cycles. This periodic action allows the high-speed data path to be achieved while the control logic operates at a lower frequency, reducing power consumption.
Data Source
AI summary
A module including a first slice and a second slice. The first slice and the second slice receive data from a plurality of inputs. A first stage of the first slice selects a first subset of the inputs in synchronization with an edge of a first clock. In synchronization with a second clock, a second stage of the first slice selects an input from the first subset. A first stage of the second slice selects a second subset of the inputs in synchronization with an edge of the second clock. In synchronization with the first clock, a second stage of the second slice selects an input from the second subset.