CMOS Nanosheet FET Pair Layout for Reduced 3D Footprint

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Solution Overview

Problem

Current 3D field effect transistor (FET) structures in integrated circuit chips face challenges at smaller technology nodes, such as increased complexity and cost, necessitating a reduction in CMOS device architectural footprint.

Innovation Solution

The formation of complementary metal-oxide semiconductor (CMOS) devices using stacked nanosheet FET pairs with a dielectric spacer dividing them, allowing for the creation of independent source/drain contacts and gate contacts, enabling a reduced footprint by fabricating CMOS devices from a single stack of nanosheet layers grown on an underlying substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If traditional 3D FET structures are used, then device functionality is maintained, but architectural footprint is increased and manufacturing complexity increases

Engineering Contradiction:

Improvearchitectural footprintVSAvoidmanufacturing complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D FET structures to vertically stacked 3D FET configurations, where multiple FET channels are stacked in the vertical dimension. This allows multiple devices to occupy a smaller planar footprint while maintaining individual device functionality through independent gate control in the vertical stack architecture.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides a single large FET into multiple smaller FET segments stacked vertically, with each segment having its own gate electrode. This segmentation enables independent control of each FET channel while reducing the overall planar footprint, as the segmented devices share common source and drain regions.

Inventive Principle:

Principle #1Segmentation

2Productivity

If technology nodes are scaled down, then device density is improved, but manufacturing complexity and cost increase

Engineering Contradiction:

Improvedevice densityVSAvoidmanufacturing complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple FET channels into a single vertical stack structure that shares common source and drain regions. This consolidation increases device density by allowing multiple functional devices to occupy the space of a single planar device, while the shared regions simplify manufacturing processes compared to fully independent devices.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The stacked FET structure provides multi-functionality by integrating multiple FET channels with different threshold voltages or device types (n-type and p-type) in a single vertical stack. This universal structure can serve multiple logical functions while occupying minimal planar space, improving device density without proportionally increasing manufacturing complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12087770B2Complementary field effect transistor devices

Publication Date: 2024.09.10 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A complementary metal-oxide semiconductor device formed by fabricating CMOS nanosheet stacks, forming a dielectric pillar dividing the CMOS nanosheet stacks, forming CMOS FET pairs on either side of the dielectric pillar, and forming a gate contact for at least one of the FETs.