CMOS Fin and Nanosheet Gate Layout for Sub-Lithographic Pitch
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down CMOS device fabrication due to limitations in creating smaller and more complex circuits, particularly in achieving efficient three-dimensional designs like FinFETs, where traditional photolithography methods struggle to produce pitches smaller than what is obtainable.
Innovation Solution
The manufacturing process involves using double-patterning or multi-patterning techniques, including photolithography and self-aligned processes, to form gate all around (GAA) transistor structures and fin field-effect transistors (FinFETs) by patterning sacrificial layers and using spacers to create nanosheets and fins on semiconductor substrates, allowing for smaller pitches and more complex circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography methods are used, then manufacturing process is simple, but pitch size cannot be reduced below certain limit
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple discrete steps (first pattern formation, spacer deposition, second pattern formation) rather than attempting to create all features in a single photolithography step. This enables pitch reduction beyond traditional limits by breaking down the complex patterning task into manageable segments that can be executed sequentially with standard equipment.
Solution Approach 2:
The patent employs preliminary action through the formation of sacrificial patterns and spacers before final device structure creation. The sacrificial patterns are deposited and patterned in advance, then used as templates for subsequent spacer formation, which in turn define the final fin and nanosheet geometries. This preliminary structuring enables precise pitch control that would be unattainable through direct photolithography alone.
2Productivity
If geometry size is reduced to increase functional density, then production efficiency increases, but fabrication challenges increase
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structures by forming fins and nanosheets that extend in the vertical dimension. The multi-layer spacer and sacrificial pattern architecture creates vertically stacked features (fin structures, nanosheets) that provide increased functional density within the same footprint, enabling continued productivity growth as geometry scales down.
Solution Approach 2:
The patent introduces intermediary structures (sacrificial patterns, spacers, mandrels) that mediate between the lithography process and final device geometry. These intermediary elements serve as temporary templates that define critical dimensions and positions, allowing precise geometric control at scaled dimensions while using standard lithography tools, thus reducing fabrication difficulty despite smaller feature sizes.
3Manufacturing precision
If three-dimensional designs like FinFETs are implemented, then functional density increases, but traditional photolithography cannot achieve required pitches
Solution Approach 1:
The patent applies dynamics by making the patterning process adaptive and iterative rather than static and single-step. The process dynamically adjusts pitch and geometry through sequential spacer deposition and sacrificial pattern removal, allowing the same base lithography step to produce multiple different pitch values by varying spacer thickness or deposition conditions, thereby maintaining design flexibility while achieving ultra-fine pitches.
Solution Approach 2:
The patent utilizes parameter changes by varying spacer material composition, deposition thickness, and etch selectivity to control final feature dimensions. By changing these process parameters rather than relying solely on lithographic resolution, the method achieves precise pitch control for three-dimensional structures while maintaining compatibility with existing photolithography tools and design rules.
Data Source
AI summary
A manufacturing method of a complementary metal-oxide-semiconductor device includes forming semiconductor fins over a semiconductor substrate; forming nanosheets over the semiconductor substrate; forming a gate structure contacting the semiconductor fins and the nanosheets, where a contact area of the gate structure with the semiconductor fins extends mostly along a (110) crystallographic surface of a semiconductor material of the semiconductor fins, and a contact area of the gate structure with the nanosheets extends mostly along a (100) crystallographic surface of a semiconductor material of the nanosheets.