CMOS Nonvolatile Memory Cell with Floating Gate Integration
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Solution Overview
Problem
Conventional nonvolatile memory integration in CMOS integrated circuits is challenging due to the need for additional manufacturing steps and increased circuit size, limiting flexibility and practicality for applications requiring fewer than 1 Kbits of memory.
Innovation Solution
A nonvolatile memory cell comprising NMOS and PMOS transistors with a floating gate, where write and erase operations are performed through tunnel currents and control gate signals, allowing for compact integration within a standard CMOS process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional nonvolatile memory is integrated into CMOS integrated circuits, then nonvolatile memory functionality is achieved, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
The patent merges the nonvolatile memory cell structure with standard CMOS transistor structures by sharing common elements such as the substrate, gate insulating films, and interlayer insulating films. The memory cell uses a combination of NMOS and PMOS transistors with floating gates that can be formed using existing CMOS fabrication processes, eliminating the need for separate nonvolatile memory manufacturing steps.
Solution Approach 2:
The invention creates a universal memory cell structure that can perform both volatile and nonvolatile memory operations using the same CMOS-compatible transistor architecture. The floating gate structure enables data retention without power while maintaining compatibility with standard CMOS logic circuits, allowing the same process to produce both logic and memory functions.
2Reliability
If conventional nonvolatile memory is integrated into CMOS integrated circuits, then nonvolatile memory functionality is achieved, but circuit size increases
Solution Approach 1:
The patent combines multiple memory cells into a compact array structure where NMOS and PMOS transistors share common substrates and insulating layers. The memory cells are arranged in a dense grid pattern with shared bit lines and word lines, reducing the overall area required compared to separate volatile and nonvolatile memory implementations.
Solution Approach 2:
The invention nests the floating gate structure within the existing CMOS transistor structure, where the floating gate is formed between the control gate and the channel region. This nested configuration allows the nonvolatile memory functionality to be embedded within the standard CMOS process layers without requiring additional lateral space.
3Reliability
If nonvolatile memory cell is designed with floating gate structure, then data retention capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The floating gate structure utilizes self-aligned formation processes where the floating gate is automatically positioned between the source and drain regions through sequential deposition and etching steps that use previous layers as alignment references. This self-alignment mechanism eliminates the need for high-precision separate positioning steps, reducing manufacturing precision requirements while ensuring proper floating gate formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables easy production of nonvolatile memory cells that can be used for tuning integrated circuits without significantly increasing chip area, while ensuring stable data retention and flexible voltage settings.
Implementation Method 1
writing of electrons into the floating gate is performed by a tunnel current flowing through a gate insulating film of the first NMOS transistor
Implementation Method 2
electrons in the floating gate are erased by a tunnel current flowing through a gate insulating film of the second PMOS transistor
Data Source
AI summary
A nonvolatile memory cell includes: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating gate as a gate, and wherein a read signal is inputted to gates of the second and third NMOS transistors, a control gate signal is inputted to a source and an n-well of the first PMOS transistor, an erase signal is inputted to a source and an n-well of the second PMOS transistor, and a write data signal is inputted to a source of the first NMOS transistor.