CMOS Logic Compatible Non-Volatile Memory Cell Structure
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Solution Overview
Problem
Conventional non-volatile memory (NVM) processes require additional processing steps and higher voltages, leading to increased manufacturing costs, lower yields, and scalability issues when integrated into CMOS devices, with existing solutions like EEPROM and flash memory facing challenges in voltage efficiency and cell density.
Innovation Solution
A CMOS Logic based NVM cell structure comprising a program transistor, select transistor, and erase transistor with a shared floating gate, using lower voltages for programming and erasing, and optimized transistor sizes to reduce erase voltage, with mechanisms like Channel Hot Electron Injection and Fowler-Nordheim Tunneling for programming and erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional NVM processes are used, then non-volatile memory functionality is achieved, but additional processing steps are required increasing manufacturing complexity and cost
Solution Approach 1:
The patent merges the NVM functionality with standard CMOS logic processes by using a single poly-silicon layer for both logic transistors and memory transistors. The memory cell is integrated within the CMOS logic circuitry, eliminating the need for separate NVM processing steps and additional poly-silicon layers, thus reducing manufacturing complexity while maintaining non-volatile memory functionality
Solution Approach 2:
The single poly-silicon layer serves dual purposes: forming gate electrodes for both logic transistors and memory transistors. This multi-functional approach allows the same material layer to perform different functions in different parts of the circuit, eliminating the need for additional specialized processing steps for NVM fabrication
2Reliability
If conventional EEPROM cell structure is used, then erase and program operations can be performed, but high voltage (>15V) is required increasing power consumption
Solution Approach 1:
The patent changes the voltage parameter from conventional high voltage (>15V) operation to low voltage (5V) operation. This is achieved by modifying the transistor structure and doping profiles to enable efficient charge injection and removal at lower voltages, thereby reducing power consumption while maintaining reliable program and erase operations
Solution Approach 2:
The patent replaces the conventional high-voltage breakdown mechanism with a low-voltage tunneling mechanism for charge injection. By using Fowler-Nordheim tunneling through a thin oxide layer, the system achieves efficient programming and erasing at 5V instead of requiring high voltage breakdown, thus substituting a high-energy mechanical process with a lower-energy quantum mechanical process
3Productivity
If stacked gate flash EEPROM is used, then programming efficiency is improved, but thin tunnel oxide creates manufacturing defects reducing wafer yield
Solution Approach 1:
The patent changes the oxide thickness parameter from thin (in stacked gate flash) to a moderate thickness that balances tunneling efficiency with manufacturing reliability. This optimized oxide thickness enables sufficient programming efficiency while reducing the likelihood of manufacturing defects and improving wafer yield
Solution Approach 2:
The patent uses a composite gate structure consisting of multiple layers including the oxide layer, poly-silicon layer, and doped regions. This composite structure provides both the tunneling efficiency needed for programming and the structural robustness required for high wafer yield, combining the benefits of thin-oxide tunneling with the stability of thicker, more manufacturable layers
4Use of energy by moving object
If split gate flash is used, then programming voltage is reduced to 12V, but cell area increases reducing storage density
Solution Approach 1:
The patent merges the select transistor and memory transistor into a shared structure where the select transistor gate also serves as the memory transistor gate. This merging eliminates the need for separate first and second gates required in split-gate flash, reducing the cell area while maintaining the ability to achieve low-voltage programming through controlled charge injection
5Use of energy by moving object
If single polysilicon EEPROM is used, then operating voltage is reduced to ±5V, but negative voltage application creates reliability issues
Solution Approach 1:
The patent inverts the voltage polarity approach by using only positive voltages (0V to 5V) instead of bipolar voltages (±5V). The erase operation is achieved by preventing charge injection (program inhibit) rather than by injecting opposite polarity charges, thus eliminating reliability issues associated with negative voltage application while maintaining low-voltage operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable, low-voltage operation with improved scalability and cost-effectiveness, reducing manufacturing complexity and increasing wafer yield while maintaining high storage density and endurance.
Implementation Method 1
Programmer transistor 210 may be used to program the memory cell, as known to those skilled in the art. For example, channel hot electron injection or Fowler-Nordheim tunneling may be used.
Implementation Method 2
Erase transistor 230 may be used to erase the memory cell, as known to those skilled in the art. For example, channel hot electron injection or Fowler-Nordheim tunneling may be used.
Data Source
AI summary
The present invention is to provide a logic based single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. A non-volatile memory cell in accordance with the present invention comprises a program transistor with a program transistor source as a first program terminal; a select transistor with a select transistor gate as a select terminal and a select transistor drain as a second program terminal; and an erase transistor with an erase transistor source and an erase transistor drain connected as an erase terminal, wherein the erase transistor shares a floating gate with the program transistor and the drain program transistor is connected to the select transistor source. By employing the present invention, significant cost advantages in feature-rich semiconductor products, such as System-on-Chip (SoC) design, compared to conventional dual-poly floating gate embedded Flash memory are provided.