CMOS and NVM Integration via Unified Gate Dielectric Formation
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Solution Overview
Problem
Current advanced logic technology requires numerous additional processing steps to integrate non-volatile memory (NVM) devices with CMOS transistors having metal gates and high-k gate dielectrics on the same integrated circuit, complicating the integration of NVM devices and CMOS devices in a replacement gate process flow.
Innovation Solution
A gate-last processing flow is used to form a tunneling gate dielectric for NVM transistors simultaneously with a gate dielectric for p-type field effect transistors, and a control gate dielectric for NVM transistors simultaneously with a gate dielectric for n-type field effect transistors, eliminating the need for additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NVM devices are integrated with CMOS transistors having metal gates and high-k gate dielectrics using conventional processes, then device functionality is achieved, but the number of processing steps increases significantly
Solution Approach 1:
The patent merges the formation of gate dielectrics for NVM devices and CMOS devices into a single unified process step. By forming the high-k gate dielectric for CMOS transistors and the tunneling gate dielectric for NVM devices simultaneously, the invention eliminates multiple sequential processing steps while achieving full device functionality integration.
Solution Approach 2:
The patent employs a universal gate dielectric formation process that serves dual purposes: creating the high-k gate dielectric for CMOS transistors and the tunneling gate dielectric for NVM devices. This multi-functional approach allows a single process to accomplish what traditionally required separate specialized steps, thereby reducing overall process complexity.
2Adaptability or versatility
If additional processing steps are added to integrate NVM devices with replacement gate CMOS devices, then device compatibility is improved, but manufacturing efficiency decreases
Solution Approach 1:
The patent performs preliminary actions by forming the gate dielectric layers for both NVM and CMOS devices during the standard replacement gate process flow, before the metal gate formation steps. This preliminary integration ensures compatibility with the replacement gate process while avoiding the need for additional post-processing steps that would reduce manufacturing efficiency.
3Reliability
If separate processing flows are used for NVM and CMOS devices, then device performance is optimized, but process complexity increases
Solution Approach 1:
The patent applies local quality by using the same unified gate dielectric formation process to create different dielectric structures in different device regions. The process forms a high-k gate dielectric for CMOS transistors in one region and a tunneling gate dielectric for NVM devices in another region, allowing each device type to maintain its optimized performance characteristics while following a single common process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient integration of CMOS and NVM devices on the same substrate without requiring extra processing steps, simplifying the fabrication process and enhancing integration efficiency.
Implementation Method 1
a first high-k gate dielectric and a first gate electrode, and first source/drain regions located within the first semiconductor material portion and laterally surrounding the first channel region
Implementation Method 2
a tunneling gate dielectric for NVM transistors is formed at the same time as a gate dielectric for n-type field effect transistors (pFETs)
Data Source
AI summary
A method that allows integrating complementary metal oxide semiconductor (CMOS) transistors and a non-volatile memory (NVM) transistor on a single substrate is provided. The NVM transistor includes a gate stack containing a high-k tunneling gate dielectric, a floating gate electrode, a high-k control gate dielectric and a control gate electrode. The high-k tunneling gate dielectric is formed form a first high-k dielectric layer employed in formation of a gate dielectric for a p-type field effect transistor (FET), the floating gate electrode is formed from a capping material layer employed in annealing the first high-k dielectric layer, and the high-k control gate dielectric is formed from a second high-k dielectric layer employed in formation of a gate dielectric for an n-type FET.