CMOS Latch-Up Prevention via N-Well Contact Zone

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Solution Overview

Problem

CMOS ICs face latch-up issues due to the formation of a PNPN path, which can cause high current flow and damage, and existing solutions are not applicable to 1P1M process CMOS manufacturing as they cannot form a conductor to connect the P+ region externally.

Innovation Solution

A CMOS structure with a PMOS and NMOS portion isolated by a P-well and N-well region, an insulation layer, and a pad structure with contact plugs penetrating through the insulation layer to interface with the N-well region, where P-type dopants are implanted to create a contact zone that breaks the PNPN path, preventing latch-up.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a P+ region is added above the P-well region to drain high current, then latch-up protection is improved, but the manufacturing process becomes incompatible with 1P1M process since no conductor can be formed to connect the P+ region externally

Engineering Contradiction:
Improvelatch-up protectionVSAvoidprocess compatibility
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent introduces an N-well region as an intermediary structure between the P-well and the external pad. This N-well acts as a mediator that can be externally connected through standard 1P1M process conductors, while still providing the necessary current drainage path to protect against latch-up. The N-well region with P-type dopants creates a controlled PN junction that diverts harmful currents without requiring direct external connection to P+ regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the electrical parameters of the N-well region by introducing P-type dopants to create a contact zone with specific electrical characteristics. This parameter change transforms the N-well from a simple isolation structure into an active protection mechanism that can drain high currents while maintaining compatibility with the 1P1M manufacturing process.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If the PNPN path is left intact for normal circuit operation, then device functionality is maintained, but latch-up can occur causing high current flow and potential damage

Engineering Contradiction:
Improvecircuit functionalityVSAvoidlatch-up damage risk
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality modification by introducing P-type dopants specifically in the contact zone of the N-well region. This localized doping creates a specific electrical property in one area (the contact zone) while leaving the rest of the N-well and P-well structures intact for normal circuit operation. The local modification provides protection against latch-up without disrupting the overall circuit functionality.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements preliminary anti-action by pre-configuring the N-well region with P-type dopants to create a protective mechanism before latch-up can occur. This preliminary structural arrangement ensures that when high current threatens to flow through the PNPN path, the pre-established N-well contact zone is already in place to drain the current and prevent latch-up damage.

Inventive Principle:
Principle #9Preliminary anti-action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively minimizes latch-up by isolating the PNPN path with P-type dopants, preventing high current flow and reducing the risk of damage to the CMOS IC.

Implementation Method 1

performing an implantation process to provide P-type dopants as an outer area of a contact zone for interfacing an inner area of the contact zone with the N-well region

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS8426922B2CMOS structure and latch-up preventing method of same
Publication Date: 2013.04.23 UNITED MICROELECTRONICS CORP
  • US8426922B2 patent drawing
  • US8426922B2 patent drawing
  • US8426922B2 patent drawing

AI summary

A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants.