CMOS Piezoelectric Oscillator Start-Up Control for Lower Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing oscillation circuits, such as those used in portable electronic devices, face high current consumption during start-up, which is not effectively addressed by existing technologies, and they struggle to operate efficiently in standby mode due to prolonged start-up times and bias stabilization requirements.
Innovation Solution
An oscillation circuit with a CMOS logic inverter and a control circuit that clamps input/output levels before start-up and supplies a pulse signal to the amplifier after the beginning of oscillation start-up, reducing start-up time and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the oscillation circuit uses a conventional design with feedback resistor and piezoelectric oscillator, then it can generate reference clock signals, but it consumes excessive current during start-up and cannot operate efficiently in standby mode
Solution Approach 1:
The control circuit performs preliminary actions by detecting the power supply voltage level and proactively managing the oscillation start-up process. When voltage rises above a first threshold, the control circuit prepares the circuit for oscillation; when it exceeds a second threshold, the control circuit stops the oscillation signal, preventing excessive current consumption during prolonged start-up while ensuring reliable oscillation establishment
Solution Approach 2:
The control circuit implements feedback mechanisms by continuously monitoring the power supply voltage and adjusting the oscillation signal accordingly. The feedback loop detects voltage thresholds and dynamically controls the oscillation start-up and stop timing, optimizing the balance between start-up reliability and current consumption efficiency
2Loss of energy
If the oscillation circuit is designed to suppress current consumption when oscillation stops, then standby mode efficiency improves, but start-up current consumption remains high
Solution Approach 1:
The control circuit dynamically adjusts its behavior based on real-time voltage conditions. It transitions the oscillation circuit from a static design to a dynamic system that adapts its operation: enabling oscillation when voltage is sufficient, and stopping it when voltage is inadequate or oscillation is established, thereby optimizing both standby efficiency and start-up power consumption
3Reliability
If the oscillation circuit allows prolonged operation during start-up to ensure stable oscillation, then oscillation reliability improves, but current consumption increases unnecessarily
Solution Approach 1:
The control circuit changes the operational parameters of the oscillation circuit based on voltage thresholds. By detecting when voltage exceeds the second threshold, the control circuit determines that sufficient power is available for stable oscillation and stops the oscillation signal, preventing unnecessary current consumption while ensuring oscillation reliability is achieved
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution allows for reduced current consumption during oscillation start-up and enables the oscillation circuit to operate efficiently in standby mode by shortening start-up time and minimizing power usage.
Implementation Method 1
an piezoelectric oscillator (12) and a feedback resistor (13) connected in parallel to an input and an output of an amplifier (11)
Data Source
AI summary
Disclosed is an oscillator in which current consumption relating to oscillation is reduced. The oscillator comprises: an amplifier to an input and output of which a piezoelectric oscillator and a feedback resistor are connected in parallel, and which is constituted by a CMOS logic inverter circuit; and a control circuit, which is constituted by a CMOS logic circuit, for clamping input/output levels of the amplifier and halting oscillation before oscillation start-up, unclamping the input/output levels at beginning of oscillation start-up and supplying a pulse signal to an output terminal of the amplifier a prescribed period of time after the beginning of oscillation start-up.


