CMOS Output Circuit for Supply Interruption Diagnosis
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Solution Overview
Problem
CMOS circuits face challenges in replicating the fault behavior of potentiometers without additional external components, particularly in maintaining diagnostic output levels during supply voltage interruptions, while ensuring low residual current and compliance with high-temperature conditions, which is technically complex and limits the circuit's application range.
Innovation Solution
The circuit arrangement uses N-channel depletion transistors connected to a control circuit and a bleeder resistor to generate defined output signals, operating independently of the rest of the circuit, with a charge pump providing a negative voltage to ensure diagnostic levels are met without limiting the load resistance or operating temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a power-down state is implemented with extremely low residual current to maintain diagnostic levels, then the diagnostic reliability is improved, but the circuit complexity increases and the overall error budget of critical analog circuit parts is compromised
Solution Approach 1:
The circuit is divided into two independent parts: the sensor signal conditioning circuit and the diagnostic circuit. The diagnostic circuit uses depletion transistors that operate independently from the main circuit, allowing diagnostic functions to be performed without affecting the main circuit's error budget or requiring complex power-down control.
Solution Approach 2:
Depletion transistors are introduced as intermediary elements between the output and the load resistor. These transistors can be controlled to create diagnostic states (pulling output to VSS or VDD) without requiring the main circuit to enter a power-down state, thus simplifying the overall control architecture.
2Use of energy by moving object
If the circuit is switched to a low-current state before supply voltage falls below a certain value, then the residual current is reduced to maintain diagnostic levels, but the control complexity under various boundary conditions increases
Solution Approach 1:
The diagnostic circuit uses the available supply voltage and load resistor to generate diagnostic states without requiring active control of the main circuit. The depletion transistors automatically create the necessary current paths when controlled by the simple diagnostic control circuit, eliminating the need for complex power-down sequencing.
Solution Approach 2:
The diagnostic function is extracted from the main circuit control logic. Instead of requiring the main circuit to enter a complex power-down state, a separate diagnostic control circuit directly controls the depletion transistors to achieve diagnostic states, simplifying the control requirements.
3Reliability
If additional circuitry measures are implemented in each individual circuit block to achieve low residual current, then the diagnostic level compliance is improved, but the integration complexity and design risk increase
Solution Approach 1:
The depletion transistors serve multiple functions: they act as switches for diagnostic states and as controlled current sources. The same diagnostic control circuit handles both VDD loss and GND loss diagnostics, eliminating the need for separate circuitry measures in different blocks.
4Use of energy by moving object
If the load resistance is limited to an unusual maximum value, then the residual current can be controlled to ensure diagnostic level compliance, but the application range of the circuit is restricted
Solution Approach 1:
The invention changes the control parameter from limiting load resistance to controlling the gate voltage of depletion transistors. By adjusting the gate voltage, the residual current can be controlled to be less than 2.5% of VDD regardless of the load resistance value, allowing the circuit to work with a wide range of load resistances and expanding the application range.
Data Source
Figure 1~2
AI summary
The invention relates to a circuit arrangement for producing a defined output signal in an CMOS integrated circuit. The aim of said invention is to develop a circuit arrangement which make it possible to carry out a robust largely independent of another circuit diagnosis of a VDD- or GND connection interruption, does not require the upper limit of a load resistance, does not limit the upper operation temperature of the integrated circuit and which can be embodied on a chip. For this purpose, the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit, the gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance, the second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS and the drain terminal of the second N channel depletion transistor is connected to a potential VDD.