CMOS Power Amplifier Bias Control for Common-Mode Linearity
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Solution Overview
Problem
Existing CMOS power amplifiers face challenges in maintaining linearity across various frequency ranges and signal levels due to variations in transconductance and common-mode supply fluctuations, leading to distortion and reduced performance.
Innovation Solution
Implementing multi-path common-mode feedback loops that dynamically adjust bias voltages and supply signals to maintain balanced transconductance and symmetrical output, using cascoded FETs and feedback networks to stabilize the common-mode voltage and supply signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single feedback loop is used to control common-mode voltage, then the circuit complexity is reduced, but the ability to maintain linearity across temperature, process, and supply voltage variations is insufficient
Solution Approach 1:
The single feedback loop is segmented into multiple parallel feedback loops, each targeting specific distortion components (second-order and third-order intermodulation products). This segmentation allows independent optimization of each loop's bandwidth and gain characteristics, enabling effective cancellation of different distortion types while maintaining overall system stability and linearity across varying conditions.
Solution Approach 2:
Distortion cancellation circuits are introduced as intermediary elements between the power amplifier and output. These circuits generate anti-phase distortion components that cancel the harmful intermodulation products, acting as mediators that preserve signal linearity without requiring complete redesign of the amplifier core structure.
2Reliability
If the feedback loop bandwidth is increased to track fast signal variations, then the linearity improvement is enhanced, but the stability of the feedback loop deteriorates
Solution Approach 1:
The feedback loops employ dynamic compensation techniques with frequency-dependent gain and phase characteristics. The cancellation circuits are designed with bandwidths optimized for their specific distortion components, allowing the system to adaptively track signal variations while maintaining stability through careful pole-zero placement and compensation network design.
Solution Approach 2:
Different feedback loops are assigned different bandwidth parameters and gain factors tailored to their specific distortion cancellation tasks. Second-order cancellation loops may use wider bandwidths while third-order loops use narrower bandwidths, optimizing each loop's performance for its target distortion type without compromising overall system stability.
3Reliability
If asymmetric biasing is used to balance transconductance, then the distortion cancellation is improved, but the circuit complexity increases
Solution Approach 1:
The biasing circuit automatically adjusts the gate voltages of the differential pair transistors based on the operating conditions and distortion levels. The circuit self-regulates to maintain optimal transconductance balance without requiring external manual adjustment or complex control logic, achieving asymmetric biasing through inherent circuit feedback mechanisms.
Data Source
AI summary
A power amplifier using multi-path common-mode feedback loops for radio frequency linearization is disclosed. In one aspect, a complementary metal oxide semiconductor (CMOS) power amplifier containing cascoded n-type field effect transistors (NFETs) and cascoded p-type FETs (PFETs) may have a common-mode feedback network and provides bias voltages that are dynamically varying with the signal power to keep the output common-mode fixed around a half-supply level, while the small-signal and large-signal transconductances of the FETs are kept balanced. A further feedback network may be associated with the supply voltage to assist in providing a symmetrical supply signal. The symmetrical supply signal allows for supply variations without introducing distortion for the power amplifier stage.