CMOS Pad Driver Slew Control Using Parasitic Gate-Drain Capacitance
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Solution Overview
Problem
In low voltage CMOS processes, existing driver circuits face challenges in achieving controlled rise/fall times and high output voltage swing due to deep submicron technology scaling, leading to issues with electromagnetic interference and signal integrity in high-speed I/O designs.
Innovation Solution
A slew-rate controlled driver circuit using PMOS and NMOS transistors with parasitic capacitance-based feedback, where current sources generate currents corresponding to the capacitance values, and level shifters adjust input signals to suitable levels for the transistors, eliminating the need for feedback capacitors and allowing for process compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If deep submicron technology scaling is used to reduce transistor voltage, then power consumption is reduced, but output voltage swing capability deteriorates
Solution Approach 1:
The patent changes the operating parameters by using transistors with different voltage ratings than the supply voltage. Specifically, it uses transistors rated for lower voltages (e.g., 2.5V) in a 3.3V system, and controls their operation through level-shifting to prevent exceeding their voltage ratings while achieving full supply voltage swing at the output.
2Device complexity
If simple driver architecture is used, then device complexity is reduced, but slew rate control capability deteriorates
Solution Approach 1:
The patent implements feedback by using the parasitic capacitance inherent in the transistor structure as a feedback element. The parasitic capacitance between gate and drain automatically senses the output voltage and provides feedback control, eliminating the need for external feedback capacitors while maintaining slew rate control.
Solution Approach 2:
The patent employs self-service by utilizing the parasitic capacitance that naturally exists in the transistor structure for slew rate control. This eliminates the need for separate external feedback capacitors, as the transistor's own parasitic elements perform the control function.
3Measurement precision
If external feedback capacitors are used for slew rate control, then slew rate precision is improved, but silicon area increases
Solution Approach 1:
The patent employs self-service by utilizing the parasitic capacitance that naturally exists in the transistor structure for slew rate control. This eliminates the need for separate external feedback capacitors, as the transistor's own parasitic elements perform the control function.
Solution Approach 2:
The patent converts the harmful parasitic capacitance, which is normally considered an unwanted effect in transistor design, into a beneficial feedback element for slew rate control. By utilizing this inherent parasitic capacitance, the patent eliminates the need for additional external capacitors.
4Object-generated harmful factors
If high voltage tolerance transistors are used, then voltage swing capability is improved, but transistor threshold voltage control becomes more difficult
Solution Approach 1:
The patent changes the operating parameters by using transistors with different voltage ratings than the supply voltage. Specifically, it uses transistors rated for lower voltages (e.g., 2.5V) in a 3.3V system, and controls their operation through level-shifting to prevent exceeding their voltage ratings while achieving full supply voltage swing at the output.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides efficient slew rate control with reduced silicon area, compensating for variations in transistor processes and supply voltage, while maintaining high voltage tolerance and minimizing electromagnetic interference.
Implementation Method 1
The PMOS transistor also has a parasitic capacitance between its gate and drain
Data Source
AI summary
A slew-rate controlled driver circuit in an integrated circuit fabricated in a low voltage CMOS process, having an input node and an output node. A PMOS pull-up transistor is provided, having a source connected to one side of a power supply, having a gate, and having a drain connected to the output node. The PMOS transistor also has a parasitic capacitance between its gate and drain, having a value that may vary from one integrated circuit to the next from process variations and in response to varying circuit conditions. A current source generates a current having a level corresponding to the value of the parasitic capacitance, and to provide that current to the gate of the PMOS transistor. A level shifter receives an input signal having a voltage varying in a first range provides as output signal to the gate of the PMOS transistor shifted to a level suitable for the PMOS transistor. An NMOS pull-down transistor is also provided, connected to the other side of the power supply, with a similar and corresponding current source and level shifter as has the PMOS transistor.