CMOS Pass-Gate Interconnects Using Low-Vt P-Channel Transistors
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Solution Overview
Problem
Interconnect delay in programmable integrated circuits, such as FPGAs, is a significant bottleneck due to the use of pass transistors, which can be mitigated by employing low threshold voltage P-channel transistors in CMOS pass-gate circuits to reduce signal delay while managing increased leakage current.
Innovation Solution
Incorporating low threshold voltage P-channel transistors in parallel with N-channel transistors within CMOS pass-gate circuits, and configuring these P-channel transistors to operate with a low threshold voltage for the CMOS process, along with back-biasing to minimize leakage current, enhances the performance of interconnect circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low threshold voltage P-channel transistors are used in CMOS pass-gate circuits, then signal delay is reduced, but leakage current increases
Solution Approach 1:
The patent combines N-channel and P-channel transistors in parallel to form a CMOS pass-gate circuit. This merging allows the circuit to leverage the complementary strengths of both transistor types: N-channel transistors provide low resistance when passing high logic levels, while P-channel transistors provide low resistance when passing low logic levels, thereby reducing overall signal delay while managing leakage characteristics through proper configuration
Solution Approach 2:
The patent changes the threshold voltage parameter of the P-channel transistor to a low threshold voltage value. This parameter change enables the P-channel transistor to conduct more effectively and reduce resistance during signal passing, directly addressing the signal delay issue. The low threshold voltage P-channel transistor can turn on more easily and conduct with lower resistance, improving signal propagation speed
2Speed
If supply voltage is increased to reduce interconnect delay, then signal delay is reduced, but power consumption increases
Solution Approach 1:
Instead of changing the supply voltage parameter, the patent changes the threshold voltage parameter of the P-channel transistor to low threshold voltage. This alternative parameter change achieves similar performance benefits (reduced resistance and delay) without the quadratic increase in dynamic power consumption that would result from raising supply voltage, since power consumption scales with V^2
3Speed
If low threshold voltage transistors are used in drivers, then signal delay is reduced, but leakage current increases significantly
Solution Approach 1:
The patent merges N-channel and P-channel transistors in a complementary CMOS configuration where each transistor type handles different logic levels. This combination allows the circuit to achieve low resistance paths for both high and low logic levels without requiring all transistors to have low threshold voltage, thereby reducing overall delay while limiting the leakage penalty to only the necessary low threshold voltage P-channel transistor in the pass-gate
Data Source
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AI summary
An exemplary interconnect circuit (200) for a programmable integrated circuit (IC) (100) includes an input terminal (218-1 ) coupled to receive from a node (204) in the programmable IC, an output terminal (220) coupled to transmit towards another node (208) in the programmable IC, first and second control terminals (222-1, 222-2) coupled to receive from a memory cell (212) of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate (202-1 ) coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor (Q2) configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC. (Fig. 2).