CMOS-Integrated Peltier Cooling Structure for Chip Hotspots
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Solution Overview
Problem
Existing semiconductor cooling devices based on the Peltier effect have a weak cooling effect and are incompatible with CMOS processes, necessitating a more effective and process-compatible cooling solution for chip circuits.
Innovation Solution
An integrated cooling device comprising alternating N-type and P-type deep doped regions connected in S-shaped structures, with metal interconnects, which facilitates efficient heat dissipation by flowing heat away from the device area, and optionally includes additional heat dissipation structures for enhanced vertical heat transfer, all compatible with existing CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal Peltier effect is used for cooling, then cooling effect is achieved, but cooling effect is weak and incompatible with CMOS processes
Solution Approach 1:
The patent changes the material parameter from metal to semiconductor, and changes the physical effect parameter from Joule heating to Peltier effect, thereby achieving both strong cooling effect and CMOS process compatibility through semiconductor doping and gate structure design
Solution Approach 2:
The patent replaces the traditional metal-based Peltier cooling mechanism with a semiconductor-based field-effect transistor structure that utilizes the Peltier effect at the semiconductor-metal interface, enabling integration with CMOS processes while maintaining effective cooling performance
2Adaptability or versatility
If traditional cooling methods are used, then process compatibility is maintained, but cooling effect is insufficient for high-speed chips
Solution Approach 1:
The patent applies local quality by creating specific doped regions (N-type and P-type) at targeted locations within the transistor structure, where the Peltier effect is maximized at the semiconductor-metal interface, providing localized efficient cooling exactly where heat is generated in the CMOS circuit
3Reliability
If additional cooling modes are added, then cooling capability is improved, but device complexity increases
Solution Approach 1:
The patent makes the field-effect transistor structure multi-functional by enabling it to perform both its traditional switching function and a cooling function simultaneously through the Peltier effect, thereby improving cooling capability without adding separate cooling modes or increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves improved heat dissipation efficiency with reduced power consumption and compatibility with CMOS processes, effectively lowering junction temperatures of chip modules while maintaining negligible power usage.
Implementation Method 1
Peltier effect refers to a phenomenon of heat absorption and heat release at joints of different conductors when current flows through a loop composed of different conductors
Data Source
AI summary
Integrated cooling device based on Peltier effect and manufacturing method thereof are provided. The device comprises one or more first heat dissipation structures around a device area. Each first heat dissipation structure comprises first N-type deep doped regions and first P-type deep doped regions arranged alternately, first vias, and first metal interconnection layers. The first vias are respectively located on two ends of each first N-type and each first P-type deep doped region. The first metal interconnect layers connect the first vias and such that the first heat dissipation structures are connected as a first S-shaped structure. When the first S-shaped structure is turned on, heat in the first N-type deep doped regions and the first P-type deep doped regions flows from a side close to the device area to its other side away from the device area, so as to realize heat dissipation in the device area.