CMOS Digital-to-Phase Converter With Linear Clock Phase Mixing
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Solution Overview
Problem
Existing digital-to-phase converters for high-speed serial communication links face challenges such as complexity, high manufacturing costs, and inaccuracy due to the use of current-mode logic (CML), which do not scale well with shrinking fabrication technology and have a nonlinear relationship between phase control and sampling clock signals.
Innovation Solution
A digital-to-phase converter circuit that includes pre-driver modules for producing complementary buffered clock signals with controlled slew rates and a mixer module forming a weighted combination of these signals based on phase control inputs, using CMOS logic to overcome the limitations of CML, thereby providing a digitally controlled phase output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current-mode logic (CML) is used in digital-to-phase converters, then the circuit can operate at high speeds, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent changes the logic family parameter from CML to CMOS, fundamentally altering the operating principles and device characteristics. This parameter change allows the circuit to achieve adequate speed performance while dramatically reducing complexity and manufacturing cost associated with CML implementation
Solution Approach 2:
The patent extracts and removes the CML-to-CMOS converter stages from the system, eliminating the complexity and cost associated with these interface circuits. By designing the digital-to-phase converter directly in CMOS, the patent takes out the unnecessary conversion interfaces
2Speed
If current-mode logic (CML) is used in digital-to-phase converters, then high-speed operation is achieved, but manufacturing cost increases
Solution Approach 1:
The patent changes the logic family parameter from CML to CMOS, fundamentally altering the operating principles and device characteristics. This parameter change allows the circuit to achieve adequate speed performance while dramatically reducing complexity and manufacturing cost associated with CML implementation
Solution Approach 2:
The patent extracts and removes the CML-to-CMOS converter stages from the system, eliminating the complexity and cost associated with these interface circuits. By designing the digital-to-phase converter directly in CMOS, the patent takes out the unnecessary conversion interfaces
3Speed
If CML circuits are used, then high-speed performance is achieved, but scalability with shrinking fabrication technology deteriorates
Solution Approach 1:
The patent changes the logic family parameter from CML to CMOS, fundamentally altering the operating principles and device characteristics. This parameter change allows the circuit to achieve adequate speed performance while dramatically reducing complexity and manufacturing cost associated with CML implementation
Solution Approach 2:
The patent makes the circuit universally compatible with standard CMOS fabrication processes, allowing it to scale with shrinking technology nodes. The CMOS-based design can be implemented across various fabrication technologies without requiring specialized CML processes
4Ease of operation
If prior digital-to-phase converters are used, then clock phase conversion is achieved, but accuracy deteriorates due to nonlinear relationship
Solution Approach 1:
The patent segments the phase control range into multiple discrete zones, each handled by a dedicated mixer cell. This segmentation allows for precise control within each zone while maintaining overall linearity across the full phase range, improving accuracy compared to prior continuous control approaches
Data Source
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AI summary
Systems and methods for converting digital signals into clock phases are disclosed. An example digital-to-phase converter circuit receives a complementary in-phase and quadrature clock signals and produces four clock outputs at a phase controlled by a digital phase control input. The digital-to-phase converter uses first and second pre-driver modules to buffer the -phase and quadrature clock signals and produce corresponding buffered clock signals having controlled slew rates. Mixer modules produce the clock outputs by forming weighted combinations of the buffered clock signals. The weighting is determined based on the phase control input. The controlled slew rates of the buffered clock signals allow digital mixer module to provide accurate phase control. The digital-to-phase converter may also include an output buffer that compensates for nonlinearities in the relationship between the phases of the clock outputs and the phase control input.